Datasheet

Current Mirror Voltage Drop Monitor
The DS3923 includes a voltage monitor that indicates
the voltage drop across the current mirror. This signal is
output on APDV. This signal should be used to accurately
maintain the correct APD bias voltage in conjunction with
the feedback resistors for the APD bias boost converter.
MIRIN MIROUT
APDV (V - V ) 2=
Current Clamp
The DS3923 has a current clamping circuit to protect the
APD by limiting the amount of current from MIROUT. The
current limit is defined by a resistor (R
LIM
) connected
between the RLIM pin and ground. A larger R
LIM
results in
a lower current clamp limit (see Electrical Characteristics
table).
Shutdown
The MIROUT output can be set to a high-impedance state
using the ISRC/SHDN pin, effectively disabling the APD.
The ISRC/SHDN pin is active-high.
Sample/Hold
As shown in the block diagram, the DS3923 Sample/Hold
consists of sampling capacitors (C
S
), control logic and a
differential output amplifier. The control logic selects the
current mirror for the sample/hold. Additionally, it controls
the sample time by taking a logic input from SENXOR pin
as shown in Figure 4. The sample/hold has a discharge
circuit to discharge parasitic capacitance on the mirror
outputs VIP1, VIP2, V
IN
and the sample capacitor before
it starts sampling.
During the sample time (t
S
) the sample/hold capacitor is
connected to sample/hold input for sampling of the input
signal either from VIP1 or VIP2 which is selected by the
sample/hold control circuit. As shown below in Figure 3,
the sampling start and stop depends upon the logic input
of SENXOR and SEN. Sampling stops at the SEN fall-
ing edge (when SENXOR is low) or rising edge (when
SENXOR is high), and the voltage stored at the sampling
capacitors is then amplified by the hold amplifier.
The voltage at current mirrors VIP1, VIP2, and IOUT pins
can be shown as:
VIP1 0.8 I1 R4= ××
VIP2 0.2 I1 R5= ××
OUT
I 0 . 1 I1 R 6= ××
I1, R4, R5, and R6 are shown in the Typical Application
Circuit.
Figure 3. SEN Pulse and Sample/Hold Output Timing Diagram
SEN
SEN
t
S
= SAMPLE TIME t
OUT
= OUTPUT TIME
t
OUT
t
OUT
t
S
SAMPLE AND HOLD
OUTPUT AVAILABLE
t
S
SENXOR = LOW
SENXOR = HIGH
DS3923 High-Speed Current Mirror
with Sample/Hold Output
www.maximintegrated.com
Maxim Integrated │ 11