Datasheet

DS3882

Dual-Channel Automotive CCFL Controller

____________________________________________________________________ 19

Table 2. Status Register 1 (SR1) [SRAM, E0h]

BIT R/W

POWER-UP

DEFAULT

NAME FUNCTION

0 R 0 FAULT_RT

Fault Condition—Real Time. A real-time bit that indicates the current operating status of

channel 1.

0 = Normal condition

1 = Fault condition

1 R 0 FAULT_L

Fault Condition—Latched. A latched bit that is set when the channel enters a fault

condition. This bit is cleared when read, regardless of the current state of fault.

2 R 0 STO_L

Lamp Strike Timeout—Latched. A latched bit that is set when the lamp fails to strike.

This bit is cleared when read.

3 R 0 OV_L

Overvoltage—Latched. A latched bit that is set when a lamp overvoltage is present for

at least 64 lamp cycles. This bit is cleared when read.

4 R 0 LOUT_L

Lamp Out—Latched. A latched bit that is set when a lamp out is detected. This bit is

cleared when read.

5 R 0 LOC_L

Lamp Overcurrent—Latched. A latched bit that is set when a lamp overcurrent is

detected. This bit is cleared when read.

6 R 0 SVML_RT

Supply Voltage Monitor Low—Real Time. A real-time bit that reports the comparator

output of the SVML pin.

7 R 0 SVMH_RT

Supply Voltage Monitor High—Real Time. A real-time bit that reports the comparator

output of the SVMH pin.

Note 1: Writing to this register has no effect on it.

Note 2: See Figure 8 for more details on how the status bits are set.

Note 3: SR1 is cleared when any of the following occurs:

• V

drops below the UVLO threshold

• the SVML or SVMH thresholds are crossed

• the PDN hardware pin goes high

• the PDNE software bit is written to a logic 1

• the channel is disabled by the CH1D control bit