Datasheet

DS3881
Single-Channel Automotive CCFL Controller
4 _____________________________________________________________________
Note 1: All voltages are referenced to ground unless otherwise noted. Currents into the IC are positive, out of the IC negative.
Note 2: During fault conditions, the AC-coupled feedback values are allowed to be below the absolute max rating of the LCM1 or
OVD1 pin for up to 1 second.
Note 3: Voltage with respect to V
DCB
.
Note 4: Lamp overdrive and analog dimming (based on reduction of lamp current) are disabled.
Note 5: This is the minimum pulse width guaranteed to generate an output burst, which will generate the DS3881’s minimum burst
duty cycle. This duty cycle may be greater than the duty cycle of the PSYNC input. Once the duty cycle of the PSYNC input
is greater than the DS3881’s minimum duty cycle, the output’s duty cycle will track the PSYNC’s duty cycle. Leaving
PSYNC low (0% duty cycle) disables the GA1 and GB1 outputs in DPWM receiver mode.
Note 6: This is the maximum lamp frequency duty cycle that will be generated at GA1 or GB1 outputs with spread-spectrum modu-
lation disabled.
Note 7: I
2
C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I
2
C standard-
mode timing.
Note 8: After this period, the first clock pulse can be generated.
Note 9: C
B
—total capacitance allowed on one bus line in picofarads.
Note 10: EEPROM write time applies to all the EEPROM memory. EEPROM write begins after a stop condition occurs.
Note 11: Guaranteed by design.
I
2
C AC ELECTRICAL CHARACTERISTICS (See Figure 9)
(V
CC
= +4.75V to +5.25V, T
A
= -40°C to +105°C, timing referenced to V
IL(MAX)
and V
IH(MIN)
.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCL Clock Frequency f
SCL
(Note 7) 0 400 kHz
Bus Free Time Between Stop and
Start Conditions
t
BUF
1.3 µs
Hold Time (Repeated) Start
Condition
t
HD:STA
(Note 8) 0.6 µs
Low Period of SCL t
LOW
1.3 µs
High Period of SCL t
HIGH
0.6 µs
Data Hold Time t
HD:DAT
0 0.9 µs
Data Setup Time t
SU:DAT
100 ns
Start Setup Time t
SU:STA
0.6 µs
SDA and SCL Rise Time t
R
(Note 9)
20+
0.1C
B
300 ns
SDA and SCL Fall Time t
F
(Note 9)
20+
0.1C
B
300 ns
Stop Setup Time t
SU:STO
0.6 µs
SDA and SCL Capacitive
Loading
C
B
(Note 9) 400 pF
EEPROM Write Time t
W
(Note 10) 20 30 ms
NONVOLATILE MEMORY CHARACTERISTICS
(V
CC
= +4.75V to +5.25V)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
EEPROM Write Cycles +85°C (Note 11) 30,000