Datasheet

DS3514
I
2
C Gamma and V
COM
Buffer with EEPROM
_______________________________________________________________________________________ 5
NONVOLATILE MEMORY CHARACTERISTICS
(V
CC
= +2.7V to +5.5V.)
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS
T
A
= +85°C (Guaranteed by design) 50,000
EEPROM Write Cycles
T
A
= +25°C (Guaranteed by design) 200,000
Writes
Note 1: All voltages are referenced to ground. Currents entering the IC are specified positive and currents exiting the IC are
negative.
Note 2: If V
CC
is less than +2.7V or is left unconnected, the DS3514 pulls the I
2
C bus to V
CC
, preventing communication with other
devices on the I
2
C bus.
Note 3: I
DD
supply current is specified with V
DD
= 15.0V and no load on V
COM
or GM1–GM14 outputs.
Note 4: I
CC
is specified with the following conditions: SCL = 400kHz, SDA = V
CC
= 5.5V, and V
COM
and GM1–GM14 floating.
Note 5: I
CCQ
is specified with the following conditions: SCL = SDA = V
CC
= 5.5V, and V
COM
and GM1–GM14 floating.
Note 6: I
DDQ
is specified with the following conditions: SCL = SDA = V
CC
= 5.5V and V
COM
and GM1–GM14 floating.
Note 7: This is the minimum V
CC
voltage that causes EEPROM to be recalled.
Note 8: This is the time from V
CC
> V
POR
and V
DD
> V
DD(MIN)
until the device is powered up.
Note 9: Integral nonlinearity is the deviation of a measured value from the expected values at each particular setting. Expected
value is calculated by connecting a straight line from the measured minimum setting to the measured maximum setting.
INL = [V(RW)
i
- (V(RW)
0
]/LSB(measured) - i, for i = 0...N (N = 255 for V
COM
, 1023 for GM1–GM14).
Note 10: Differential nonlinearity is the deviation of the step-size change between two LSB settings from the expected step size. The
expected LSB step size is the slope of the straight line from measured minimum position to measured maximum position.
DNL = [V(RW)
i+1
- (V(RW)
i
]/LSB(measured) - 1, for i = 0...(N - 1) (N = 255 for V
COM
, 1023 for GM1–GM14).
Note 11: Specified with the V
COM
and gamma bias currents set to 100% (CR.5 = 1, CR.4 = 0).
Note 12: EEPROM data is assumed already settled at input of Latch B. LD transitions after EEPROM byte has been selected.
Note 13: Rising transition from 5V to 10V; falling transition from 10V to 5V.
Note 14: I
2
C interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I
2
C
standard-mode timing.
Note 15: C
B
—total capacitance of one bus line in picofarads.
Note 16: EEPROM write time begins after a STOP condition occurs.
Note 17: Pulses narrower than max are suppressed.
8-BIT
DAC
0.1μF
2.2Ω
0 TO 1.5V
50kHz
C
D
= 1μF
80h
VRH V
DD
V
COM
V
COM
VRL
DS3514
Figure 1. V
COM
Settling Timing Diagram