Datasheet

DS3514
I
2
C Gamma and V
COM
Buffer with EEPROM
16 ______________________________________________________________________________________
Control Register 48h: Control Register (CR)
FACTORY DEFAULT 20h
MEMORY TYPE NV
48h x x BIAS1 BIAS0 x x MODE1 MODE0
BIT 7 BIT 0
Bits 7:6 Reserved
Bits 5:4
V
COM
and Gamma Bias Current Control Bits (BIAS[1:0]):
00 = 60%
01 = 80%
10 = 100% (default)
11 = 150%
Bits 3:2 Reserved
Bits 1:0
DS3514 Mode (MODE[1:0]):
00 = S0/S1 pins are used to select the desired bank (A–D) (default).
01 = SOFT S0/S1 (bits) are used to select the desired bank (A–D).
1X = Latch A is used to control the DACs.
Status Bits Register 4Ah: Real-Time Indicator of Logic State on LD, S1, and S0 Pins
FACTORY DEFAULT —
MEMORY TYPE Read Only
4Ah LD x x x x x S1 S0
BIT 7 BIT 0
This is an example of how the bits are arranged for a typical GDATx memory location. GDATx has 10 bits that are
arranged in two consecutive bytes. The following example shows the arrangement for GM1 GDAT1 (58h–59h). This
arrangement is applicable for all the EEPROM data for all gamma channels.
GDATx Register: EEPROM Data for the Gamma Channels
FACTORY DEFAULT 8000h
MEMORY TYPE NV
58h GDAT[9] GDAT[8] GDAT[7] GDAT[6] GDAT[5] GDAT[4] GDAT[3] GDAT[2]
59h GDAT[1] GDAT[0] x x x x x x
BIT 7 BIT 0