Datasheet
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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For T1 structured-with-CAS, multiply the above formula by 0.75.
The jitter buffer depth is defined by the Rx_max_buff_size param
eter found in the Bundle Configuration Tables.
When the jitter buffer level reaches the value of Rx_max_buff_size,
an overrun situation is declared.
The Rx_PDVT param
eter (also found in the Bundle Configuration Tables) defines the amount of data to be stored
in the jitter buffer to compensate for network delay variation. This parameter has two implications:
Rx_PDVT def
ines the chip’s immunity to the Ethernet network delay variation.
The data arriving from the network is delayed by Rx_PDVT befo
re it is read out of the jitter buffer and
forwarded to the framer..
Rx_PDVT m
ust be smaller than Rx_max_buff_size. Also, the difference between Rx_max_buff_size and Rx_PDVT
must be larger than the time that it takes to create a packet (otherwise an overrun may occur when the packet
arrives). Typically, the recommended value for Rx_max_buff_size is 2*
Rx_PDVT + PCT (packet creation time).
This provides equal immunity for both delayed and bursty packets.
Configuring the jitter buffer parameters correctly avoids underrun and overrun situations. Underrun occurs when
the jitter buffer becomes empty (the rate data is entering the buffer is slower than the rate data is leaving). When an
underrun occurs the TDMoP block transmits conditioning data instead of actual data towards the TDM interface.
The conditioning data is specified by the Receive SW Conditioning Octet Select table fo
r TDM data and the
location specified by Rx_CAS_src (S
DRAM or Receive SW CAS) for signaling. Overrun occurs when the jitter
buffer is full and there is no room for new data to enter (the rate data is leaving the buffer is slower than the rate
data is entering). Underrun and overrun require special treatment from the TDMoP hardware, depending on the
bundle type.
Figure 10-48. Jitter Buffer Parameters
The JBC uses a 64 by 32 bit Bundle Timeslot Table to identify th
e assigned timeslots of each active bundle. The
index to the table is the bundle number. The CPU must configure each active bundle entry (setting a bit means that
the corresponding timeslot is assigned to this bundle). For unstructured bundles, the whole bundle entry (all 32
bits) must be set.
Jitter buffer statistics are stored in a 256-entry table called the Jitter Buffer Status Table. Each TDM port has 3
2
dedicated entries, one per timeslot. This table stores the statistics of the active jitter buffer for each active bundle. A
configurable parameter called Jitter_buffer_index lo
cated in the timeslot assignment tables (section 11.4.5) points
to the entry in the Jitter Buffer Status Table wh
ere the associated jitter buffer statistics are stored. The value of the
Jitter_buffer_index sh
ould be set as follows: