Datasheet
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Figure 10-47. Timing in TDM-over-Packet
The jitter buffer, located in the SDRAM, has two main roles:
Compensate for packet delay variation
Provide fill level information as the independent variable used by the clock recovery machines to
reconstruct the TDM clock on a slave TDMoP device.
The data enters the buffer at a variable rate determined by packet arrival times and leaves it at a constant TDM
rate. In clock recovery mode, the amount of data in the jitter buffer (the “fill level”) steers the clock recovery
mechanism.
10.6.10.2
Jitter Buffer Configuration
Separate areas are allocated in the external SDRAM for TDM data and for signaling, as described in section
10.6.9.
In low-spe
ed mode (High_speed=0 in
General_cfg_reg0) both data and signaling areas are divided into eight
identical sections, one for each E1/T1/Nx64 interface. These section are further divided as follows:
In E1/T1 structured mode, each per-port data section contains the data of 32 timeslots for E1 or 24
timeslots for T1 (a total of 32*8=256 timeslots for all eight interfaces). Each E1/T1 timeslot is allocated a
maximum of 4 kB of space (128kB per interface and a total of 1024 kB for all eight interfaces).
Each signaling section is divided into multiframe sectors, with each sector containing the signaling nibbles
of up to 32 timeslots (total of 64 kB for all 8 interfaces).
In serial interface mode or E1/T1 unstructured mode, there is no per-timeslot allocation. The jitter buffer is
divided into eight identical sections, one for each interface (each section is 512 kB for HDLC bundles or
128 kB for other bundle types).
In high-speed mode (E3, T3, STS-1), the jitter buffer is arranged as one large buffer without division into sections
(total of 512 kB).
The Jitter Buffer maximum depth in time units (seconds) is calculated according to the following formula:
½ x Buffer area per interface x
Rate
8
where:
½ = Two halves of the buffer
Buffer area per interface = 512 kB for a single high-speed interface or 128 kB for a low-speed interface
8 = Number of bits per byte
Rate = Transmission rate (e.g., 2.048 Mbps)