Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Table 10-14. IPv6 Header Fields (L2TP
v3) .............................................................................................................. 60
Table 10-15. Control Word Fields............................................................................................................................. 60
Table 10-16. RTP Header Fields.............................................................................................................................. 61
Table 10-17. VCCV OAM Payload Fields................................................................................................................. 62
Table 10-18. UDP/IP-Specific OAM Payload Fields................................................................................................. 63
Table 10-19. CAS – Supported Interface Connections for AAL1 and CESoPSN .................................................... 68
Table 10-20. CAS Handler Selector Decision Logic................................................................................................. 69
Table 10-21. AAL1 Header Fields ............................................................................................................................ 72
Table 10-22. SDRAM Access Resolution ................................................................................................................. 79
Table 10-23. SDRAM CAS Latency vs. Frequency.................................................................................................. 79
Table 10-24. Buffer Descriptor First Dword Fields (Used for all Paths) ................................................................... 85
Table 10-25. Buffer Descriptor Second Dword Fields (TDM  ETH and CPU  ETH).......................................... 86
Table 10-26. Buffer Descriptor Second Dword Fields (ETH  CPU) ...................................................................... 86
Table 10-27. Buffer Descriptor Third Dword Fields (ETH  CPU) .......................................................................... 87
Table 10-28. Start of an 802.3 Pause Packet........................................................................................................... 97
Table 10-29. Handling IPv4 and IPv6 Packets ......................................................................................................... 98
Table 10-30. TDMoIP Port Number Comparison for TDMoIP Packet Classification ............................................. 100
Table 10-31. Bundle Identifier Location and Width................................................................................................. 100
Table 10-32. Registers Related to the Elastic Store............................................................................................... 108
Table 10-33. Elastic Store Delay After Initialization................................................................................................ 109
Table 10-34. T1-SF Framing Pattern and Signaling Bits........................................................................................ 111
Table 10-35. T1-ESF Framing Pattern and Signaling Bits ..................................................................................... 112
Table 10-36. SLC-96 Framing Pattern and Signaling Bits ..................................................................................... 112
Table 10-37. E1 CRC-4 Multiframe Framing Pattern ............................................................................................. 114
Table 10-38. Registers Related to Setting Up the Framer and Formatter.............................................................. 114
Table 10-39. Registers Related to the Transmit Synchronizer............................................................................... 115
Table 10-40. Registers Related to Signaling .......................................................................................................... 116
Table 10-41. Timeslot Number Schemes ............................................................................................................... 116
Table 10-42. Registers Related to T1 Transmit BOC............................................................................................. 118
Table 10-43. Registers Related to T1 Receive BOC.............................................................................................. 119
Table 10-44. Registers Related to Legacy T1 Transmit FDL ................................................................................. 119
Table 10-45. Registers Related to Legacy T1 Receive FDL .................................................................................. 119
Table 10-46. Registers Related to Maintenance and Alarms................................................................................. 121
Table 10-47. T1 Alarm Criteria ............................................................................................................................... 122
Table 10-48. E1 Alarm Criteria ............................................................................................................................... 123
Table 10-49. E1 LOF Sync and Resync Criteria .................................................................................................... 123
Table 10-50. T1 Line Code Violation Counting Options ......................................................................................... 124
Table 10-51. E1 Line Code Violation Counting Options......................................................................................... 124
Table 10-52. T1 Path Code Violation Counting Options......................................................................................... 125
Table 10-53. T1 Frames Out Of Sync Counting Options........................................................................................ 125
Table 10-54. Registers Related to DS0 Monitoring ................................................................................................ 125
Table 10-55. Registers Related to Framer and Payload Loopbacks...................................................................... 126
Table 10-56. Registers Related to T1 In-Band Loop Code Generator ................................................................... 127
Table 10-57. Registers Related to T1 In-Band Loop Code Detection .................................................................... 128
Table 10-58. Registers Related to SLC96.............................................................................................................. 128
Table 10-59. LIU External Components ................................................................................................................. 134
Table 10-60. Transformer Specifications................................................................................................................ 135
Table 10-61. Pseudorandom Pattern Generation................................................................................................... 145
Table 10-62. Repetitive Pattern Generation ........................................................................................................... 145
Table 11-1. Top-Level Memory Map....................................................................................................................... 150
Table 11-2. Global Registers .................................................................................................................................. 151
Table 11-3. TDMoP Memory Map .......................................................................................................................... 159
Table 11-4. TDMoP Configuration Registers.......................................................................................................... 160
Table 11-5. TDMoP Status Registers ..................................................................................................................... 160
Table 11-6. Counters Types ................................................................................................................................... 184
Table 11-7. CPU Queues ....................................................................................................................................... 191
Table 11-8. Jitter Buffer Status Table..................................................................................................................... 197
Table 11-9. Bundle Timeslot Table......................................................................................................................... 197