Datasheet
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Figure 10-32. CAS Transmitted in the Ethernet-to-TDM Direction
CAS JITTER BUFFERS IN SDRAM
TDM1_TSIG_CTS
PORTn
RECEIVE
LINE CAS
TABLES
Framer
TRANSMIT
CAS BITS
INTERNAL
REGISTE
R
CP
U
MANIPULATED
CAS BITS
(PER TIMESLOT)
TDMoP
SELECTOR
PORTn
RECEIVE
SW
CAS
TABLES
CAS BITS
CAS
HANDLER
INTERRUPT ON CHANGE
PORTn
RECEIVE
LINE (NEXT
MF) CAS
TABLES
TDM2_TSIG_CTS
TDM3_TSIG_CTS
TDM4_TSIG_CTS
TDM5_TSIG_CTS
TDM6_TSIG_CTS
TDM7_TSIG_CTS
TDM8_TSIG_CTS
The Receive SW CAS tabl
es contain CAS bits written by CPU software.
Each port’s Receive Line CAS table (se
ction 11.4.10) is updated with the CAS bits stored in the Receive Line (Next
MF) CAS table when the TDMn_TX_MF_CD signal is asserted to indicate the multiframe boundary. For E1 ports,
CAS bits are updated every 2 milliseconds. For T1 SF ports, CAS bits are updated every 1.5 milliseconds. For T1
ESF ports, CAS bits are updated every 3 milliseconds.
There is a Receive Line CAS table fo
r each TDM port. These tables hold the CAS information extracted from
received packets and subsequently transmitted on TDMn_TSIG signals toward the framers. Each table contains 32
rows, and each row holds the CAS bits of one timeslot. Only the first 24 rows are used for T1 interfaces. For E1
and T1 ESF interfaces, each row holds the A, B, C and D bits. For T1 SF interface where only the A and B bits
exist, each row holds the A and B bits duplicated i.e. A, B, A, B.
If CAS bits change in the Receive Line CAS table,
a per-timeslot interrupt is asserted. The Rx_CAS_change
registers in the Error! Reference source not found. indicate which timeslots have changed CAS bits. Upon
notification that CAS bits have changed, CPU software can read the CAS bits from the Receive Line (Next MF)
CAS table, manipulate them and then write them directly into the framer’s internal transmit signaling registers (TS1
to TS16). In
this case, the framer should be configured to use the CAS information from its CAS registers and not
from its TSIG inputs.
The bits in each Receive Line CAS table
are sent to the Framer on the TDMn_TSIG signal, as shown in the figures
below.