Datasheet
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
67 of 366
10.6.5
CAS Handler
10.6.5.1
CAS Handler, TDM-to-Ethernet Direction
In the TDM-to-Ethernet direction, the CAS handler receives the CAS bits (for structured-with-CAS AAL1 or
CESoPSN bundles) on the TDMn_RSIG_RTS signal. Depending on the value of the per-bundle Tx_CAS_source
config
uration bit in the Bundle Configuration Tables, the CAS
handler inserts either the CAS bits from the
corresponding TDMn_RSIG_RTS signal or the values from the transmit SW CAS tables (section 11.4.9) into the
AAL1 or CE
SoPSN packets, in order to deliver the signaling as part of the AAL1 or CESoPSN payload packets.
See Figure 10-26.
The tran
smit SW CAS tables may contain conditioning bits set by CPU software during configuration (per timeslot).
If CAS bits received on the TDMn_RSIG_RTS signal change, a per-timeslot maskable interrupt is asserted. The
Tx_CAS_change re
gisters in the Error! Reference source not found. indicate which timeslots have changed CAS
bits. The Tx_CAS_change_mask
registers are available to selectively mask these interrupts. Upon notification that
CAS bits have changed, the CPU can read the CAS bits directly from the framer’s receive signaling registers (RS1
to RS16), alte
r them if needed, and write them into the TDMoP block’s transmit SW CAS tables.
Figure 10-26. CAS Transmitted in the TDM-to-Ethernet Direction
CAS
HANDLER
TRANSMIT
SW
CAS
TABLES
FRAMER
RECEIVE
CAS
BITS
INTERNAL
REGISTER
CPU
MANIPULATED
CAS
BITS
(P E R
TIMESLOT )
CONDITIONING
BITS
TDMoP
AAL1/CESoPSN
PACKETS
IN
SDRAM
TDM1_RSIG_RTS
TDM2_RSIG_RTS
TDM3_RSIG_RTS
TDM4_RSIG_RTS
TDM5_RSIG_RTS
TDM6_RSIG_RTS
TDM7_RSIG_RTS
TDM8_RSIG_RTS
There is a transmit SW CAS table for each TDM port. Each table consists of 4 rows, and each row contains the
CAS bits of eight timeslots. For ports configured for E1, timeslots 1–15 and 17–31 are used and timeslots 0 and 16
are meaningless. For ports configured for T1, timeslots 0–23 are used and timeslots 24–31 are meaningless. Ports
configured for T1 SF have two copies of A and B CAS bits arranged A, B, A, B. Other port types have one copy of
bits A, B, C and D. These cases are illustrated in Figure 10-27 an
d Figure 10-28.