Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Figure 10-48. Jitter Buffer Parameters
..................................................................................................................... 82
Figure 10-49. TDM-over-Packet Data Flow Diagram ............................................................................................... 84
Figure 10-50. Free Buffer Pool Operation ................................................................................................................ 88
Figure 10-51. TDM-to-Ethernet Flow........................................................................................................................ 89
Figure 10-52. Ethernet-to-TDM Flow........................................................................................................................ 90
Figure 10-53. TDM-to-TDM Flow.............................................................................................................................. 91
Figure 10-54. TDM-to-CPU Flow .............................................................................................................................. 92
Figure 10-55. CPU-to-TDM Flow.............................................................................................................................. 93
Figure 10-56. CPU-to-Ethernet Flow ........................................................................................................................ 94
Figure 10-57. Ethernet-to-CPU Flow ........................................................................................................................ 95
Figure 10-58. Ethernet MAC..................................................................................................................................... 96
Figure 10-59. Format of TDMoIP Packet with VLAN Tag......................................................................................... 99
Figure 10-60. Format of TDMoMPLS Packet with VLAN Tag .................................................................................. 99
Figure 10-61. Format of TDMoMEF Packet with VLAN Tag .................................................................................... 99
Figure 10-62. Structure of Packets with Trailer ...................................................................................................... 102
Figure 10-63. Interrupt Pin Logic ............................................................................................................................ 105
Figure 10-64. LIU, Framer and BERT Interrupt Information Flow Diagram............................................................ 107
Figure 10-65. CRC-4 Recalculate Method ............................................................................................................. 128
Figure 10-66. Receive HDLC Servicing Example................................................................................................... 131
Figure 10-67. Transmit HDLC Servicing Example.................................................................................................. 133
Figure 10-68. LIU External Components, Longitudinal Protection ......................................................................... 134
Figure 10-69. T1/J1 Transmit Pulse Templates ..................................................................................................... 137
Figure 10-70. E1 Transmit Pulse Templates .......................................................................................................... 137
Figure 10-71. Typical Rx Monitor Application......................................................................................................... 138
Figure 10-72. Jitter Tolerance, T1 Mode ................................................................................................................ 139
Figure 10-73. Jitter Tolerance, E1 and 2048kHz Modes........................................................................................ 139
Figure 10-74. Jitter Attenuation .............................................................................................................................. 141
Figure 10-75. Analog Loopback.............................................................................................................................. 141
Figure 10-76. Local Loopback ................................................................................................................................ 142
Figure 10-77. Remote Loopback ............................................................................................................................ 142
Figure 10-78. Dual Loopback ................................................................................................................................. 143
Figure 10-79. PRBS Synchronization State Diagram............................................................................................. 146
Figure 10-80. Repetitive Pattern Synchronization State Diagram.......................................................................... 147
Figure 10-81. LIU + Framer Connections ............................................................................................................... 148
Figure 11-1. 16-Bit Addressing ............................................................................................................................... 149
Figure 11-2. 32-Bit Addressing ............................................................................................................................... 149
Figure 11-3. Partial Data Elements (shorter than 16 bits) ...................................................................................... 149
Figure 11-4. Partial Data Elements (16 to 32 bits long).......................................................................................... 150
Figure 12-1. JTAG Block Diagram.......................................................................................................................... 320
Figure 12-2. JTAG TAP Controller State Machine ................................................................................................. 321
Figure 14-1. Receive Framer Timing Using the RCLKF Pin................................................................................... 327
Figure 14-2. Receive Framer Timing Using the RCLK Pin..................................................................................... 328
Figure 14-3. Receive Framer Timing, Elastic Store Enabled ................................................................................. 328
Figure 14-4. Receive Framer Timing, Line Side with LIU Not Used....................................................................... 328
Figure 14-5. Transmit Formatter Timing Using the TCLKF Pin.............................................................................. 329
Figure 14-6. Transmit Formatter Timing, Elastic Store Enabled ............................................................................ 330
Figure 14-7. Transmit Formatter Timing, Line Side with LIU Not Used.................................................................. 330
Figure 14-8. RST_SYS_N Timing........................................................................................................................... 330
Figure 14-9. CPU Interface Write Cycle Timing ..................................................................................................... 331
Figure 14-10. CPU Interface Read Cycle Timing ................................................................................................... 331
Figure 14-11. SPI interface Timing (SPI_CP = 0)................................................................................................... 332
Figure 14-12. SPI interface Timing (SPI_CP = 1)................................................................................................... 332
Figure 14-13. SDRAM Interface Write Cycle Timing .............................................................................................. 333
Figure 14-14. SDRAM Interface Read Cycle Timing.............................................................................................. 334
Figure 14-15. TDMoP TDM Timing, One-Clock Mode (Two_clocks=0, Tx_sample=1) ......................................... 335
Figure 14-16. TDMoP TDM Timing, One Clock Mode (Two_clocks=0, Tx_sample=0) ......................................... 336
Figure 14-17. TDMoP TDM Timing, Two Clock Mode (Two_clocks=1, Tx_sample=1, Rx_sample=1) ................. 336
Figure 14-18. TDMoP TDM Timing, Two Clocks Mode (Two_clocks=1, Tx_sample=0, Rx_sample=0) ............... 336