Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
54 of 366
RESET FUNCTION LOCATION COMMENTS
HDLC Receive Reset RHC.RHR This bit resets the Receive HDLC controller.
HDLC Transmit Reset THC1.THR This resets the Transmit HDLC controller.
Elastic Store Receive Reset RESCR.RESR This bit resets the Receive Elastic Store.
Elastic Store Transmit Reset TESCR.TESR This bit resets the Transmit Elastic Store.
Bit Oriented Code Receive
Reset
RBOCC.RB
R This bit resets the Receive BOC controller.
Loop Code Integration Reset RDNCD1, RUPCD1
Writing to these registers resets the programmable in-
band code integration period.
Spare Code Integration Reset RSCD1
Writing to this register resets the programmable in-band
code integration period.
The device has several features included to reduce power consumption. The individual LIU transmitters can be
powered down by setting the TPDE bit in the LIU maintenance control register (LMCR). Not
e that powering down
the transmit LIU results in a High-Z state for the corresponding TTIP and TRING pins, and reduced operating
current. The RPDE in the LMCR
register can be used to power down the LIU receiver.
The LMCR.TXEN (T
ransmit Enable) bit (per-port) or the TXENABLE pin (all ports) can be used to disable the TTIP
and TRING outputs and place them in a high-impedance mode while keeping the LIU transmitter(s) in an active
state (powered up). The TXENABLE pi
n has priority over the TXEN bit. These controls are useful for equipment
protection switching applications.
10.6 TDM-over-Packet Block
10.6.1 Packet Formats
To transport TDM data through packet switched networks, the TDM-over-Packet block encapsulates the TDM data
into Ethernet frames as depicted in Figure 10-10.