Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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In addition to producing 38.88 MHz for the adaptive clock recovery machines, CLAD1 also make E1 and T1 master
clocks for the LIUs and Framers. CLAD1 can make these E1 and T1 master clocks from the CLK_HIGH sig
nal if
available. This is not affected by the state of the GCR1.CLK_
HIGHD bit. If a clock is not applied to the CLK_HIGH
pin because clock recovery is disabled, CLAD1 must have a 2.048MHz or 1.544MHz signal on the MCLK pin
from
which to make the E1 and T1 master clocks. In this case, MCLK
must be enabled by setting GCR1.MCLKE, and
the frequency of the MCLK
signal must be specified by GCR1.MCLKS. The signal on MCLK should have ±50ppm
or better accuracy for E1 or ±32ppm or better for T1 to meet the line rate frequency accuracy requirements of
various telecom standards documents.
The TDM-over-packet block also requires a 50 MHz or 75 MHz clock (50 ppm or better) to clock its internal
circuitry and the SDRAM interface (SD_CLK). Whe
n the CLK_SYS_S pin is low, a 50 MHz or 75 MHz clock applied
to the CLK_SYS pin is passed directly to the TDMoP block. When the CLK_SYS_S pin i
s high, a 25 MHz clock on
the CLK_SYS pin i
s internally multiplied by an analog PLL in the CLAD2 block to either 50 MHz or 75 MHz as
specified by GCR1.SYSCLKS.
10.5 Reset and Power-Down
A hardware reset is issued by forcing the RST_SYS_N pin low. This pin resets the TDM-over-Packet block, the
MAC, and all framers, LIUs and BERTs. Note that not all registers are cleared to 0x00 on a reset condition. The
register space must be reinitialized to appropriate values after hardware or software reset has occurred. This
includes setting reserved locations to 0. A variety of block-specific resets are also available, as shown in Table
10-5.
Table 10
-5. Reset Functions
RESET FUNCTION LOCATION COMMENTS
Hardware Device Reset RST_SYS_N Pin
Transition to a 200us or more logic 0 level resets the
device. CLK_SYS and CLK_HIGH/MCLK are
recommended to be stable 200us before transitioning
out of reset.
Hardware JTAG Reset JTRST_N Pin Resets the JTAG test port.
Resets TDMoP TX, RX paths Rst_reg
Used to reset the transmit (TX) and receive (RX) paths
of the TDM-over-Packet block.
Resets the SDRAM controller General_cfg_reg0 The Rst_SDRAM_n bit resets the SDRAM controller.
Resets the BERTs GTRR.BSRST
This bit resets the Bit Error Rate Testers (BERTs) for all
ports.
Global Framer and Resets GTRR.FSRST
This bit resets the Framers (transmit and receive) for all
ports.
LIU Interface Reset GTRR.LIRST[8:1]
These bits reset the clock recovery state machine and
re-center the jitter attenuator FIFO pointers for the
corresponding LIUs.
LIU Software Resets GTRR.LSRST[7:0]
These bits reset the logic and registers for the
corresponding LIUs.
Framer Receive Reset RMMR.SFTRST This bit resets the Receive Framer.
Framer Transmit Reset TMMR.SFTRST This bit resets the Transmit Framer.