Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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 The first bit on SPI_MOSI and SPI_MISO is re
served (don’t care).
 The master then transmits two opcode bits on SPI_MOSI. The
se bits specify a read, write or status
command. The value 00b represents a status command. At the same time, the slave transmits the opcode
bits of the previous command on SPI_MISO.

The master then transmits 4 don’t care bits on SPI_MOSI. Du
ring these clock periods the slave transmits 4
bits on SPI_MISO. The firs
t 3 SPI_MISO bits are don’t-care. The 4
th
bit is a status bit that indicates whether
the last access was completed successfully (1) or is still in progress (0). The 0 value indicates that the last
access has not yet completed and that another status command must follow (see section 10.3.4.3).

Status=1 indicates that the last access was completed successfully. If the last access was a read then 32
bits of data follow on SPI_MISO,
starting from D31 (MSB) and ending with D0 (LSB). During these 32 clock
cycles, the master transmits 32 don’t-care bits on SPI_MOSI. If
the last access was a write the during the
next 32 clock cycles both the master and the slave must transmit don’t-care bits to complete the status
command. These 32 bits should be ignored.
 Status=0 indicates that the last access was not completed and that another status command must follow.
During the next 32 clock cycles both the master and the slave must transmit don’t-care bits to complete the
status command. These 32 bits should be ignored.
 The master ends the write access by deasserting SPI_SEL_N.
The total num
ber of SPI_CLK cycle
s for a status command is 40.
Table 10-4. SPI Status Command Sequence
Bit Number SPI_MOSI SPI_MISO
1 Don’t care Don’t care
2–3 opcode 00 (status) Previous access opcode
4 Don’t care Don’t care
5 Don’t care Don’t care
6 Don’t care Don’t care
7 Don’t care Don’t care
8 Don’t care Status bit: 1=access has finished, 0=access has not finished
9–40* Don’t care* Data*
* only if previous access was a read (previous access opcode = 10b).
10.4 Clock Structure
When clock recovery is enabled (Clock_recovery_en=1 in 1General_cfg_reg0), the clock recovery machines of the
TDM-over-packet block require a 38.88MHz clock. This clock can come directly from the CLK_HIGH pin
, or the
CLAD1 block (see Figure 6-1) ca
n convert a 10MHz, 19.44MHz or 77.76MHz clock on CLK_HIGH to 38.88MHz
using an analog PLL. The frequency of CLK_HIGH m
ust be specified in GCR1.FREQSEL.
When common clock (differential) mode is enabled (RTP_timestamp_generation_mode=1 in General_cfg_reg1),
the clo
ck recovery block requires a clock on the CLK_CMN pin i
n addition to the clock on the CLK_HIGH pin. See
the CLK_CMN pin de
scription for recommendations for the frequency of this clock. Often the same clock signal can
be applied to both CLK_CMN and CLK_HIGH, for example 19.4
4MHz.
When clock recovery is disabled (Clock_recovery_en=0 in
1General_cfg_reg0), CPU software can disable the
38.88MHz clock output from CLAD1 to save power by setting GCR1.CLK_H
IGHD. Clock recovery must be enabled
whenever the TDMoP block must recover one or more service clocks from received packets using either adaptive
mode or common clock (differential) mode.