Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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signals in CPU bus mode (including being active low). For a read access, all four of these bits should be 1.
At the same time, the slave transmits the byte enable values of the previous access on SPI_MISO.

The next bit on SPI_MOSI and SPI_MISO is re
served (don’t care).
 The next 24 bits the master transmits on SPI_MOSI
are address bits, starting from A24 (MSB) and ending
with A1 (LSB). At the same time, the slave transmits the address bits of the previous access on SPI_MISO.

Next the master transmits 8 don’t care bits on SPI_MOSI. Duri
ng these clock periods the slave transmits 8
bits on SPI_MISO. The firs
t 7 SPI_MISO bits are don’t-care. The 8
th
bit is a status bit that indicates whether
the current read access was completed successfully (1) or is still in progress (0). Status=0 indicates that
the current operation has not yet completed and that the status command must follow (see section
10.3.4.3).

Status=1 indicates that the current read was completed successfully and 32 bits of data follow on
SPI_MISO, starting fro
m D31 (MSB) and ending with D0 (LSB). During these 32 clock cycles, the master
transmits 32 don’t-care bits on SPI_MOSI.

Status=0 indicates that the current read was not completed and that the status command must follow (see
section 10.3.4.3). Duri
ng the next 32 clock cycles both the master and the slave must transmit don’t-care
bits to complete the read command. These 32 bits should be ignored.
 The master ends the write access by deasserting SPI_SEL_N.
The total num
ber of SPI_CLK cycle
s for a read command is 72.
Table 10-3. SPI_ Read Command Sequence
Bit Number SPI_MOSI SPI_MISO
1 Reserved Reserved
2–3 opcode 10 (read) Previous access opcode
4 1 Previous access H_WR_BE3_N value
5 1 Previous access H_WR_BE2_N value
6 1 Previous access H_WR_BE1_N value
7 1 Previous access H_WR_BE0_N value
8 Reserved Reserved
9–32 Address [24 to 1] Previous access Address [24 to 1]
33–39 Don’t care Idle (7 bits)
40 Don’t care Status bit: 1=access has finished, 0=access has not finished
41–72 Don’t care Data (32 bits)
10.3.4.3 Status Command
The status command differs from read or write commands, since it does not initiate an internal access. Usually a
status command follows a read or write command that was not completed as described above.
The SPI status command proceeds as follows:
 The SPI master (CPU) starts a status command by asserting SPI_SEL_N (l
ow).
 Then, during each SPI_CLK cy
cle a SPI_MOSI data bit is transmitted by the master (CPU), while a
SPI_MISO bit is tran
smitted by the slave (the device).