Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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signals in CPU bus mode (including being active low). At the same time, the slave transmits the byte
enable values of the previous access on SPI_MISO.

The next bit on SPI_MOSI and SPI_MISO is re
served (don’t care).
 The next 24 bits the master transmits on SPI_MOSI
are address bits, starting from A24 (MSB) and ending
with A1 (LSB). At the same time, the slave transmits the address bits of the previous access on SPI_MISO.

The next 32 bits the master transmits on SPI_MOSI are
32 bits of data, starting from D31 (MSB) and
ending with D0 (LSB). At the same time, the slave transmits 32 don’t-care bits on SPI_MISO.

Finally the master transmits 8 don’t care bits on SPI_MOSI. Durin
g these clock periods the slave transmits
8 bits on SPI_MISO. The firs
t 7 SPI_MISO bits are don’t-care. The 8
th
bit is a status bit that indicates
whether the last access was completed successfully (1) or is still in progress (0). The 0 value indicates that
the current operation has not yet completed and that the status command must follow (see section
10.3.4.3).

The master ends the write access by deasserting SPI_SEL_N.
The total num
ber of SPI_CLK cycle
s for a write command is 72. This is summarized in Table 10-2.
Table 10-2. SPI Write Command Sequence
Bit Number SPI_MOSI SPI_MISO
1 Reserved Reserved
2–3 opcode 01 (write) Previous access opcode
4 H_WR_BE3_N value Previous access H_WR_BE3_N value
5 H_WR_BE2_N value Previous access H_WR_BE2_N value
6 H_WR_BE1_N value Previous access H_WR_BE1_N value
7 H_WR_BE0_N value Previous access H_WR_BE0_N value
8 Reserved Reserved
9–32 Address [24 to 1] Previous access address [24 to 1]
33–64 Data (32 bits) Don’t care (32 bits)
65–71 Don’t care (7 bits) Idle (7 bits)
72 Don’t care (1 bit) Status bit: 1=access has finished, 0=access has not finished
10.3.4.2 Read Command
The SPI read command proceeds as follows:
 The SPI master (CPU) starts a write access by asserting SPI_SEL_N (lo
w).
 Then, during each SPI_CLK cy
cle a SPI_MOSI data bit is transmitted by the master (CPU), while a
SPI_MISO bit is tran
smitted by the slave (the device).
 The first bit on SPI_MOSI and SPI_MISO is re
served (don’t care).
 The master then transmits two opcode bits on SPI_MOSI. The
se bits specify a read, write or status
command. The value 10b represents a read command. At the same time, the slave transmits the opcode
bits of the previous command on SPI_MISO.

The next four bits the master transmits on SPI_MOSI are byte
-enable values: byte_en_3, byte_en_2,
byte_en_1, and byte_en_0 which are equivalent to the function of the H_WR_BE3_N to H_WR_BE0_N