Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Figure 10-5. Write Access to the SDRAM, 16-Bit Bus
DAT_32_16_N[0]
H_CS_N[0]
H_AD[24:1]
H_R_W_N[0]
H_READY_N[0]
[0]
H_D[15:8]
H_D[7:0]
H_WR_BE1_N[0]
H_WR_BE0_N[0]
valid
data ignored
SDRAM WRITE ACCESS
16 bit data bus
In 16-bit bus mode, read accesses to SDRAM are always 16 bits, as in Figure 10-6.
Figure 10-6. Rea
d Access to the SDRAM, 16-Bit Bus
DAT_32_16_N[0]
H_CS_N[0]
H_AD[24:1]
H_R_W_N[0]
H_READY_N[0]
[0]
H_D[15:8]
H_D[7:0]
H_WR_BE1_N[0]
H_WR_BE0_N[0]
valid
valid
SDRAM READ ACCESS
16 bit data bus
10.3 SPI Interface
The device optionally can be accessed by an external CPU through a Serial Peripheral Interface (SPI). To
configure the device for SPI interface mode, the H_CPU_SPI_N
pin must be low when the RST_SYS_N (system
reset) pin is deasserted. In SPI mode, some of the parallel CPU bus pins take on an SPI-related function while the
rest are disabled. See the CPU interface section of Table 9-1 for d
etails. The device functions as an SPI slave.
10.3.1 SPI Operation
The SPI is a 4-wire, full-duplex, synchronous interface. The SPI connects an SPI master (which initiates the data
transfer) and an SPI slave.
The SPI signal wires are as follows:
 SPI_CLK is the clo
ck for the serial data (gated clock).
 SPI_MOSI is maste
r data output, slave data input.