Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsLinear ICsDS34T108GN+

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108

46 of 366

The write access to the SDRAM is different than the write access to the chip. The SDRAM can be written with byte

resolution using the four byte write enables. In contrast, internal chip resources are always written at full CPU data

bus width (32 bits in Figure 10-2). The write byte enab

le signals should always be asserted when writing to internal

device registers.

For 32-bit CPU bus width, H_AD[1] is ig

nored, since accesses are always on an even 4-byte boundary.

Figure 10-3 shows a re

ad access to the SDRAM followed by a read access to the internal chip resources. Read

accesses always occur at CPU data bus width and the H_WR_BE pins are no

t used (and must be held high). Bytes

that are not needed by the CPU can be ignored.

Figure 10-3. Read Access, 32-Bit Bus

DAT_32_16_N[0]

H_CS_N[0]

H_AD[24:1]

H_R_W_N[0]

H_READY_N[0]

[0]

H_D[31:0]

H_WR_BE3_N[0]

H_WR_BE2_N[0]

H_WR_BE1_N[0]

H_WR_BE0_N[0]

cpu_addr[1]='don't care' cpu_addr[1]='don't care'

valid valid

SDRAM READ ACCESS

32bit cpu data bus

Figure 10-4 shows

a write access to the chip followed by a read access in 16-bit bus mode. In this mode the

H_AD[1]

signal is used because accesses are on an even 2-byte boundary. Write access to the SDRAM can still

be at byte resolution, as illustrated in Figure 10-5.

Figure 10-4. Rea

d/Write Access, 16-Bit Bus