Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
45 of 366
Table 10-1. CPU Data Bus Widths
DAT_32_16_N
Value
Dat
a Bus
Width
Access to
Chip Internal
Resources
Access to
SDRAM
Data Bus
Bits
MSB
H_WR_BE
Pins Used
1 32 bits 32 bit only 8, 16, 32 bit H_D[31:0] H_D[31] 3:0
0 16 bits 16 bit only 8, 16 bit H_D[15:0] H_D[15] 1:0
Burst accesses are not supported. The device uses the big-endian byte order, as explained in section 11.1.
The CPU starts
an access to the device by asserting the H_CS_N
signal (active low), accompanied by the desired
read/write state on H_R_W_N, add
ress on H_AD[24:1], write byte enables on the H_WR_BE pins and valid data
(for a write access) on the H_D[31:0] pin
s. In response, the device asserts H_READY_N to indicate that the access
has been carried out. The ready assertion indicates that data from the CPU has been written into the device
register or external SDRAM (for write access) or that valid data from register/SDRAM is present on the data bus
(for read access). In response to H_READY_N
assertion, the CPU de-asserts H_CS_N. This causes the chip to
de-assert H_READY_N, and there
by finish the CPU access.
In order to make CPU operation more efficient, the device immediately asserts H_READY_N du
ring a write access.
On successive accesses (write or read) H_READY_N is a
sserted only after the previous write has been completed.
In 32-bit bus mode, H_WR_BE0_N through H_WR_BE3_N
serve as write byte enable signals, replacing the
functionality of H_AD[1:0]
in the address bus. In 16-bit bus mode, H_WR_BE0_N and H_WR_BE1_N serve as
write byte enables, replacing the functionality of H_AD[0] in the ad
dress bus. These signals enable byte-resolution
write access to the external SDRAM.
When performing a write access to internal chip resources, all H_WR_BE
pins should be asserted since write
access to device registers must be done at the full bus width only.
Examples of read and write accesses on 32- and 16-bit buses are shown in the figures below.
Figure 10-2. Write Access, 32-Bit Bus
DAT_32_16_N[0]
H_CS_N[0]
H_AD[24:1]
H_R_W_N[0]
H_READY_N[0]
[0]
H_D[31:24]
H_D[23:16]
H_D[15:8]
H_D[7:0]
H_WR_BE3_N[0]
H_WR_BE2_N[0]
H_WR_BE1_N[0]
H_WR_BE0_N[0]
cpu_addr[[1]='don't care' cpu_addr[1]='don't care' cpu_addr[1]='don't care'
data ignored valid valid
data ignored valid valid
valid data ignored valid
data_ignored data ignored valid
SDRAM WRITE ACCESS SDRAM WRITE ACCESS
32 bit data bus
INTERNAL
Figure 10-2 shows two wri
te accesses to the SDRAM, one to a byte (at address 2) and the other to a word (at
addresses 0 and 1), followed by a write access to the internal chip resources.