Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
44 of 366
10 Functional Description
10.1 Power-Supply Considerations
Due to the dual-power-supply nature of the device, some I/Os have parasitic diodes between a 1.8V supply and a
3.3V supply. When ramping power supplies up or down, care must be taken to avoid forward-biasing these diodes
because it could cause latchup. Two methods are available to prevent this. The first method is to place a Schottky
diode external to the device between the 1.8V supply and the 3.3V supply to force the 3.3V supply to be within one
parasitic diode drop below the 1.8V supply (i.e. VDD3.3 > VDD1.8 – 0.4V). The second method is to ramp up the
3.3V supply first and then ramp up the 1.8V supply.
10.2 CPU Interface
The CPU interface enables an external CPU to configure and control the device and collect statistics from the
device. The CPU interface block identifies accesses (read or write) to on-chip registers and to external SDRAM,
forwards accesses to the proper place, and replies to the CPU with the requested data during read accesses. See
Figure 10-1. AC timing for
the CPU interface is specified in section 14.3.
Figure 10-1. CPU Interface Functional Diagram
CPU
SDRAM
ADDRESS
DATA
CONTROL
CPU INTERFACE
DS34T10x
CPU BUS
ACCESS
WITHIN CHIP
SDRAM
CONTROLLER
H_INT[1:0]
To configure the device for CPU interface mode, the H_CPU_SPI_N pin
must be high when the RST_SYS_N
(system reset) pin is deasserted. The chip can be configured for 16-bit or 32-bit data bus width by wiring the
DAT_32_16_N pin a
s shown in Table 10-1: