Datasheet
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
41 of 366
PIN NAME
(1)
TYPE
(2)
PIN DESCRIPTION
H_WR_BE2_N /
SPI_SEL_N
I
H_WR_BE2_N: Host Write Enable Byte 2 (Active Low)
In 32-bit parallel interface mode during a write access this pin specifies whether or
not byte 2 (H_D[15:8])
should be written to the device. In 16-bit parallel interface
mode this pin is ignored and should be pulled high or low.
0 = write byte 2
1 = don’t write byte 2
SPI_SEL: SPI Chip Select (Active Low)
In SPI interface mode this pin must be asserted (low) to read or write internal
registers.
H_WR_BE3_N /
SPI_CI
I
H_WR_BE3_N: Host Write Enable Byte 3 (Active Low)
In 32-bit parallel interface mode during a write access this pin specifies whether or
not byte 3 (H_D[15:8])
should be written to the device. In 16-bit parallel interface
mode this pin is ignored and should be pulled high or low.
0 = write byte 3
1 = don’t write byte 3
SPI_CI: SPI Clock Invert
In SPI interface mode this pin specifies the polarity of the SPI_CLK pin. See the
timing diag
rams in Figure 14-11 and Figure 14-12 for details
.
0 = SPI_CLK is normally lo
w and pulses high (leading edge is rising edge)
1 = SPI_CLK
is normally high and pulses low (leading edge is falling edge)
H_READY_N O
8mA
Host Ready Output (Active Low)
In parallel interface mode the device pulls this pin low during a read or write
access to signal that the device is ready for the access to be completed. The host
processor should not pull
H_CS_N high (inactive) to complete the access until the device
has pulled H_READY_N low.
This pin requires the use of an external pull-up resistor. The device actively drives
this pin high before allowing it to go high-impedance. See Figure 14-9.
H_INT[1:0] O
8mA
Host Interrupt Outputs (Active Low)
H_INT[0] indicates interrupt requests from the TDMoP block. H_INT[1] indicates
interrupt requests from the LIU, framer and BERT. Optionally, the H_INT[1] signal
can be forced inactive at the H_INT[1] pin and internally ORed into the H_INT[0]
signal by setting GCR1.IP
OR=1. This allows H_INT[0] to indicate interrupt
requests from any and all sources in the device. When GCR1.IPI0=1, H_INT[0] is
force
d high (inactive). When GCR1.IPI1=
1, H_INT[1] is forced high (inactive). See
section 10.9.