Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
38 of 366
PIN NAME
(1)
TYPE
(2)
PIN DESCRIPTION
MII_RXD[3:0] I
MII Receive Data Inputs
In MII mode, receive data comes from the PHY four bits at a time on MII_RXD[3:0],
on the rising edge of CLK_MII_RX. See the timing dia
gram in Figure 14-23.
In RMII mode
, receive data comes from the PHY two bits at a time on
MII_RXD[3:2] and is latched on the rising edge of CLK_MII_TX. MII_RXD[1:0] are
not use
d. See the timing diagram in Figure 14-25.
In SSMII mod
e, received data comes from the PHY one bit at a time on
MII_RXD[0] (SSMII_RXD) on the rising edge of CLK_MII_RX. MII_RXD[1]
(SSMII_RX_
SYNC) indicates 10-bit segment alignment of the serial data stream.
MII_RX_DV I
MII Receive Data Valid Input
In MII mode, this pin serves as the receive data valid input. In RMII mode, carrier
sense and receive data valid alternate on this pin. See the RMII spec for details. In
SSMII mode this pin is not used and should be pulled low or high.
MII_RX_ERR I
MII Receive Error Input
In MII mode and RMII mode, this pin serves as the receive error input. In SSMII
mode this pin is not used and should be pulled low or high.
MII_COL I
MII Collision Input
In MII mode this pin serves as the collision detection input. In RMII mode and
SSMII mode this pin is not used and should be pulled low or high.
MII_CRS I
MII Carrier Sense Input
In MII mode this pin serves as the carrier sense input. In RMII mode and SMII
mode this pin is not used and should be pulled low or high.
MDC O
8mA
PHY Management Clock Output
This signal is the clock for the Ethernet PHY management interface, which
consists of MDC and MDIO. See the timing diag
ram in Figure 14-21.
MDIO IOpu
8mA
PHY Management Data Input/Output
This signal is the serial data signal for the Ethernet PHY management interface,
which consists of MDC and
MDIO. When MDIO is an output, it is updated on the
rising edge of MDC. When MDIO is an input, it is latched into the device on the
rising edge of MDC. See the timing diagram in Figure 14-21.