Datasheet
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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PIN NAME
(1)
TYPE
(2)
PIN DESCRIPTION
present on the TDMn_RX pin. This pulse must be repeated every N*125s where
N is a positive integer (example: if N=16, it pulses every 2ms).
In one-clock mode, this signal is ignored and TDMn_TX_SYNC sp
ecifies frame
alignment for both the transmit and receive interfaces of the TDMoP engine.
Port[n]_cfg_reg.Two
_clocks specifies two-clock mode (1) or one-clock mode (0).
This pin is only active in external mode (GCR1.MODE
=1).
See the timing diagrams in Figure 14-15 through Figure 14-20.
TDMn_RSIG_RTS
Ipu
TDMoP Receive Signaling Input
When the interface type is configured for E1 or T1, the transmit signaling function
of this pin is active.
In two-clock mode, this signal is clocked by TDMn_RCLK.
In one-clo
ck mode, this signal, is clocked by TDMn_TCLK.
TDMoP Req
uest To Send Input
When the interface type is configured for serial, the request-to-send function of this
pin is active. In this mode, the real-time status of this pin can be read from
Port[n]_stat_reg1.RTS
_P.
Port[n]_cfg_reg.Two
_clocks specifies two-clock mode (1) or one-clock mode (0).
Port[n]_cfg_reg.Int_type specifie
s serial (00), E1 (01) or T1 (10) interface type.
This pin is only active in external mode (GCR1.MODE
=1).
See the timing diagrams in Figure 14-15 through Figure 14-20.
Table 9-6. SDRAM Interface Pins
PIN NAME
(1)
TYPE
(2)
PIN DESCRIPTION
SD_CLK O
8mA
SDRAM Clock
All SDRAM interface pins are updated or latched on the rising edge of SD_CLK.
See the timing diagrams in Figure 14-13 and Figure 14-14.
SD_D[31:0] IO
8mA
SDRAM Data
MSB is SD_D[31].
SD_DQM[3:0] O
8mA
SDRAM Byte Enable Mask
SD_DQM[0] is associated with the least significant byte. SD_DQM[3] is associated
with the most significant byte. When a SD_DQM pin is high during a write cycle,
the associated byte is not written to SDRAM. When a SD_DQM pin is high during
a read cycle, the associated byte is not driven out of the SDRAM (the SD_D pin
s
remain high-Z).
SD_A[11:0] O
8mA
SDRAM Address Bus
MSB is SD_A[11].
SD_BA[1:0] O
8mA
SDRAM Bank Select Outputs
The external SDRAMs used by the device have their memory organized into four
banks. These pins specify the bank to be accessed. The bank must be specified
on the same SD_CLK edg
e that the row information is specified on SD_A[11:0].
SD_CS_N O
8mA
SDRAM Chip Select (Active Low)
Driven low by the device to initiate a memory access (read or write) to the external
SDRAM.
SD_WE_N O
8mA
SDRAM Write Enable (Active Low)
Driven low by the device when data is to be written to the external SDRAM. Left
high when data is to be read from the external SDRAM.
SD_RAS_N O
8mA
SDRAM Row Address Strobe (Active Low)
Driven low by the device during SD_CLK cycles in which SD_A[11:0] indicate
s the
SDRAM row address.
SD_CAS_N O
8mA
SDRAM Column Address Strobe (Active Low)
Driven low by the device during SD_CLK cycles in which SD_A[11:0] indicate
s the
SDRAM column address.