Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
35 of 366
PIN NAME
(1)
TYPE
(2)
PIN DESCRIPTION
positive integer (example: if N=16, it pulses every 2ms).
Port[n]_cfg_reg.Two
_clocks specifies two-clock mode (1) or one-clock mode (0).
This pin is only active in external mode (GCR1.MODE
=1).
See the timing diagrams in Figure 14-15 through Figure 14-20.
TDMn_TX_MF_CD
IOpd
TDMoP Transmit Multiframe Sync Input
When the interface type is configured for E1 or T1, multiframe sync is provided to
the TDMoP engine from this pin. The signal on this pin must pulse high for one
TDMn_TCLK cycle
when the first bit the multiframe is expected to be present on
the TDMn_TX pin.
TDMoP Tra
nsmit Carrier Detect Output
When the interface type is configured for serial, the carrier detect function of this
pin is active. When Port[n]_cfg_reg.
CD_en=1, the state of this pin is controlled by
the value stored in Port[n]_cfg_reg.CD.
Port[n]_cfg_reg.Int_type=specifie
s serial (00), E1 (01) or T1 (10).
Port[n]_cfg_reg.Int_type=specifie
s serial (00), E1 (01) or T1 (10) interface type.
This pin is only active in external mode (GCR1.MODE
=1).
See the timing diagrams in Figure 14-15 through Figure 14-20.
TDMn_TSIG_CTS
O
8mA
TDMoP Transmit Signaling Output
When the interface type is configured for E1 or T1, the transmit signaling function
of this pin is active. Functional timing is shown in Figure 10-33 and Figure 10-34.
TDMoP Cle
ar to Send Output
When the interface type is configured for serial, the clear-to-send function of this
pin is active. In this mode, the state of this pin is controlled by the value stored in
Port[n]_cfg_reg.CTS.
Port[n]_cfg_reg.Int_type specifie
s serial (00), E1 (01) or T1 (10) interface type.
This pin is only active in external mode (GCR1.MODE
=1).
See the timing diagrams in Figure 14-15 through Figure 14-20.
TDMn_RCLK Ipu
TDMoP Receive Clock Input
In two-clock mode, this signal clocks the receive TDM interface of the TDMoP
engine: TDMn_RX, TDMn_RX_SYNC a
nd TDMn_RSIG_RTS.
In one-clo
ck mode, this signal is ignored, and the TDMn_TCLK sig
nal clocks both
the transmit and receive interfaces of the TDMoP engine.
Port[n]_cfg_reg.Two
_clocks specifies two-clock mode (1) or one-clock mode (0).
Port[n]_cfg_reg.Rx_
sample specifies latching on the rising (1) or falling (0) edge.
TDM1_RCLK (port 1) is used in high speed E3/T3/STS1 mode.
This pin is only active in external mode (GCR1.MODE
=1).
See the timing diagrams in Figure 14-15 through Figure 14-20.
TDMn_RX Ipu
TDMoP Receive Data Input
Serial data to the TDMoP engine is input on this pin.
In two-clock mode, this signal is clocked by TDMn_RCLK.
In one-clo
ck mode, this signal, is clocked by TDMn_TCLK.
Port[n]_cfg_reg.Two
_clocks specifies two-clock mode (1) or one-clock mode (0).
TDM1_RX (port 1) is used in high speed E3/T3/STS1 mode.
This pin is only active in external mode (GCR1.MODE
=1).
See the timing diagrams in Figure 14-15 through Figure 14-20.
TDMn_RX_SYNC
Ipd
TDMoP Receive Frame/Multiframe Sync Input
In two-clock mode, this signal is clocked by TDMn_RCLK and sp
ecifies frame or
multiframe alignment for the receive interface of the TDMoP engine. The signal on
this pin must pulse high for one TDMn_RCLK cycle
when the first bit of a frame is