Datasheet
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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For the applications above, apply the following layout considerations:
Provide termination on all high-speed interface signals and clock lines.
Provide impedance matching on long traces to prevent reflections.
Keep the clock traces away from all other signals to minimize mutual interference.
In RMII mode, a very low skew clock buffer/driver is recommended to maximize the timing budget. In this
mode it is recommended to keep all traces as short as possible.
In SSMII mode there are two clock signals, one for each direction (Rx and Tx), routed together with the
sync and data signals. Since the delay between the clock and these signals is lower, the designer can
apply a longer trace delay in this mode. Keep data/sync traces and clock traces at the same length to
maximize the timing budget.
15.3
Implementing Clock Recovery in High Speed Applications
For the high-speed interface (up to 51.84 MHz), an external clock multiplier and jitter attenuator are needed. Clock
recovery in high-speed applications is depicted below:
Figure 15-8. External Clock Multiplier for High Speed Applications
The clock multiplier converts the low speed clock at ACLK to a clock at the frequency of the emulated high-speed
circuit. The multiplication factor in the external clock multiplier must be 12 for an E3 or T3 interface and 10 for an
STS-1 interface. The clock multiplier should be tuned to add minimal jitter. The jitter attenuator can be part of the
LIU or an independent component.
15.4
Connecting a Motorola MPC860 Processor
The device is easily connected to a Motorola MPC860 processor by means of the MPC860 GPCM (General
Purpose Chip Select Machine) module.
15.4.1
Connecting the Bus Signals
Since the MPC860 address bus MSb is always 0 while the DS34T10x address bus LSb is always 0, the signal
order can be reversed as shown in the following figures.
LIU
with Jitter Attenuato
r
Tx CLK
Clock Multiplier
InOut
DS34T10x
A
CLK