Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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PIN NAME
(1)
TYPE
(2)
PIN DESCRIPTION
the cross-connect side) side of the elastic store. In E1 mode, RIOCR.RSMS2
specifies whether RMSYNCn pulses on CAS (0) or CRC-4 (1) multiframe
boundaries.
RLOFn/RLOSn O
8mA
GCR1.LOSS=0 configures this pin to be RLOFn while LOSS=1 configures it to be
RLOSn.
RLOFn: Receive Loss of Frame Output
RLOFn indicates when the receive framer is searching for frame and multiframe
alignment in the incoming data stream. See section 10.11.6.
RLOSn
: Receive Loss of Signal Output
RLOSn indicates when the receive framer detects a loss-of-signal condition. See
section 10.11.6.
Table 9-5. TDM-over-Packet Engine TDM Interface Pins
In this table, the transmit direction is the packet-to-TDM direction while the receive direction is the TDM-to-packet direction. See Figure 6-1,
Figure 6-2, Figure 8-2 and Figure 8-3.
PIN NAME
(1)
TYPE
(2)
PIN DESCRIPTION
TDMn_ACLK O
8mA
TDMoP Recovered Clock Output
The clock recovered by the TDMoP clock recovery machine is output on this pin.
TDM1_ACLK (port 1) is used in high speed E3/T3/STS1 mode.
TDMn_TCLK Ipu
TDMoP Transmit Clock Input
This signal clocks the transmit TDM interface of the TDMoP engine. Depending on
the value of Port[n]_cfg_reg.tx_sample, outputs TDMn_TX and TDMn_TSIG_CTS
are up
dated on the either the rising edge (0) or falling edge (1) of TDMn_TCLK.
Inputs TDMn_TX_SYNC a
nd TDMn_TX_MF_CD are latched on the opposite
edge. See the timing diagrams in Figure 14-15 a
nd Figure 14-16.
In one-clo
ck mode, TDMn_TCLK also clocks the receive TDM interface of the
TDMoP engine. Depending on the value of Port[n]_cfg_reg.tx_samp
le, outputs
TDMn_RX, TDMn_RX_SYNC a
nd TDMn_RSIG_RTS are updated on the either
the rising edge (0) or falling edge (1) of TDMn_TCLK.
Port[n]_cfg_reg.Two
_clocks specifies two-clock mode (1) or one-clock mode (0).
This pin is only active in external mode (GCR1.MODE
=1).
Only TDM1_TCLK (port 1) is used in high speed E3/T3/STS1 mode
(General_cfg_reg0.Hig
h_speed=1).
See the timing diagrams in Figure 14-15 through Figure 14-20.
TDMn_TX O
8mA
TDMoP Transmit Data Output
Serial data from the TDMoP engine is output on this pin.
This signal is clocked by TDMn_TCLK.
Only TDM1
_TX (port 1) is used in high speed E3/T3/STS1 mode (i.e. when
General_cfg_reg0.
High_speed=1).
This pin is only active in external mode (GCR1.MODE
=1).
See the timing diagrams in Figure 14-15 through Figure 14-20.
TDMn_TX_SYNC Ipd
TDMoP Transmit Frame Sync Input
Frame sync information is provided to the TDMoP engine from this pin. In two-
clock mode, this signal specifies only transmit frame sync. In one-clock mode, this
signal specifies frame sync for both the transmit and receive directions.
The signal on this pin must pulse high for one TDMn_TCLK cy
cle when the first bit
of a frame is expected to present on the TDMn_TX pi
n (and the TDMn_RX pin in
one-clock mode). This pulse must be repeated every N*125s where N is a