Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Figure 14-6. Transmit Formatter Timing, Elastic Store Enabled
TSYSCLK
TSER
TSYNC
11
t
SU
t
SL
t
SH
t
SP
t
SU
t
HD
t
Hd
NOTES:
1. TSER is only sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled.
Figure 14-7. Transmit Formatter Timing, Line Side with LIU Not Used
TCLKO
TDATF
t
CL
t
CH
t
CP
t
D3
14.3 CPU Interface Timing
Table 14-5. CPU Interface AC characteristics
PARAMETER SYMBOL MIN TYP MAX UNITS
RST_SYS_N Active Low Pulse Width T5 50
s
H_CS_N Deasserted or H_R_W_N Low to H_D[31:0]
High-Z
T22 16.2 ns
H_READY_N Active Pull-Up Pulse Width T26 2.9 6.8 ns
Latest of H_WR_BEx_N Asserted or H_CS_N Asserted
to H_D[31:0] Valid
T31 0 ns
H_CS_N Deasserted to H_D[31:0] Not Valid T32 0 ns
H_CS_N Asserted to H_AD[24:1] Valid T33 0 ns
H_CS_N Deasserted to H_AD[24:1] Not Valid T34 0 ns
H_CS_N Asserted to H_R_W_N Valid T35 0 ns
H_CS_N Deasserted to H_R_W_N Not Valid T36 0 ns
H_CS_N Deasserted to H_READY_N High T37 12 ns
H_CS_N Deasserted to H_WR_BEx_N[3:0] Not Valid T40 0 ns
Delay Between Two Successive Accesses T43 1.5 Internal
CLK_SYS
cycles
H_D[31:0] Valid before H_READY_N Active Low T44 1.5 ns
NOTE: The output timing specified assumes 50 pF load.
Figure 14-8. RST_SYS_N Timing
RST_SYS_N
T5