Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Table 12-1. JTAG Instruction Codes
Instructions Selected Register Instruction Codes
SAMPLE/PRELOAD Boundary Scan 010
BYPASS Bypass 111
EXTEST Boundary Scan 000
CLAMP Bypass 011
HIGHZ Bypass 100
IDCODE Device Identification 001
SAMPLE/PRELOAD. A mandatory instruction for the IEEE 1149.1 specification. This instruction supports two
functions. The digital I/Os of the device can be sampled at the Boundary Scan register without interfering with the
normal operation of the device by using the Capture-DR state. SAMPLE/PRELOAD also allows the device to shift
data into the Boundary Scan register via JTDI using the Shift-DR state.
EXTEST. EXTEST allows testing of all interconnections to the device. When the EXTEST instruction is latched in
the instruction register, the following actions occur. Once enabled via the Update-IR state, the parallel outputs of
all digital output pins are driven. The Boundary Scan register is connected between JTDI and JTDO. The Capture-
DR samples all digital inputs into the Boundary Scan register.
BYPASS. When the BYPASS instruction is latched into the parallel Instruction register, JTDI connects to JTDO
through the one-bit Bypass Test register. This allows data to pass from JTDI to JTDO not affecting the device’s
normal operation.
IDCODE. When the IDCODE instruction is latched into the parallel Instruction register, the Identification Test
register is selected. The device identification code is loaded into the Identification register on the rising edge of
JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially
via JTDO. During Test-Logic-Reset, the identification code is forced into the instruction register’s parallel output.
The device ID code always has a one in the LSB position. The device ID codes are listed in Table 12-2.
Table 12-2. JTAG ID Co
de
ID Code (hex)
Device
Rev[31:28] Device ID [27:12] Manu[11:0]
DS34T108 0 0093 143
DS34T104 0 0092 143
DS34T102 0 0091 143
DS34T101 0 0090 143
HIGHZ. All digital outputs are placed into a high impedance state. The Bypass Register is connected between
JTDI and JTDO.
CLAMP. All digital outputs pins output data from the boundary scan parallel output while connecting the Bypass
Register between JTDI and JTDO. The outputs do not change during the CLAMP instruction.
JTAG Test Registers
IEEE 1149.1 requires a minimum of two Test registers; the Bypass register and the Boundary Scan register. An
optional Test register has been included in the device design. This Test register is the Identification register and is
used in conjunction with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller.
Bypass Register. This is a single one-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ
instructions, which provides a short path between JTDI and JTDO.