Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108

320 of 366

JTAG Information

For the latest JTAG model, search under http://www.maxim-ic.com/tools/bsdl/.

JTAG Description

The device supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public

instructions included are HIGHZ, CLAMP and IDCODE. See Figure 12-1 for a

block diagram. The device contains

the following items which meet the requirements set by the IEEE 1149.1 Standard Test Access Port and Boundary

Scan Architecture:

Test Access Port (TAP) TAP Controller

Instruction Register Bypass Register

Boundary Scan Register Device Identification Register

The Test Access Port has the necessary interface pins, namely JTCLK, JTRST_N, JTDI, JTDO, and

JTMS.

Details on these pins can be found in Table 9-10. Details on the Bounda

ry Scan Architecture and the Test Access

Port can be found in IEEE 1149.1-1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994.

Figure 12-1. JTAG Block Diagram

JTDI JTMS JTCLK JTRST JTDO

TEST ACCESS PORT

CONTROLLER

Vdd Vdd Vdd

BOUNDRY SCAN

BYPASS

INSTRUCTION

IDENTIFICATION

MUX

SELECT

OUTPUT ENABLE

10K 10K 10K

JTAG TAP Controller State Machine Description

This section covers the details on the operation of the Test Access Port (TAP) Controller State Machine. See

Figure 12-2 for detail

s on each of the states described below. The TAP controller is a finite state machine which

responds to the logic level at JTMS on the risi

ng edge of JTCLK.