Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Table 9-4. Framer TDM Interface Pins
PIN NAME
(1)
TYPE
(2)
PIN DESCRIPTION
TCLKFn I
Transmit Clock Input to Formatter
This pin is only active in external mode (GCR1.MO
DE=1). In this mode, TCLKFn is
the 1.544MHz or 2.048MHz clock that clocks the transmit formatter. When the
transmit elastic store is disabled (TESCR.TESE=
0), TSERn and
TSYNCn/TSSYNCn a
re latched on the falling edge of TCLKFn. (When the elastic
store is enabled, these signals are clocked into the elastic store on the falling edge
of TSYSCLKn and out of the ela
stic store on the falling edge of TCLKFn.) See the
timing diagram in Figure 14-5. TCLKFn
is internally inverted when
TIOCR.TCLK
INV=1.
TSYSCLKn/
ECLKn
I
TSYSCLKn: Transmit System Clock Input
This pin is only active in external mode (GCR1.MODE
=1). When the transmit
elastic store is enabled (TESCR.TESE=
1), TSERn and TSYNCn/TSSYNCn are
clocked into system side (i.e. the cross-connect side) of the transmit elastic store
on the falling edge of TSYSCLKn. (Data is clocked out of the transmit elastic store
on the falling edge of TCLKFn.) See the timing diag
ram in Figure 14-6. TSYSCLK
is configured for 1.544MHz or 2.048MHz mode using TIOCR.TSCL
KM. When the
transmit elastic store is disabled, this pin should be tied low.
ECLKn: External Reference Clock Input
This pin provides an external reference clock that can be used to clock the transmit
direction of port n. In one-clock mode (GCR1.CLKM
ODE=0) it can also be used to
clock the receive direction of port n.
TSERn I
Transmit Serial Data Input
This pin is only active in external mode (GCR1.MODE
=1). When the transmit
elastic store is disabled (TESCR.TESE=
0), serial data on TSERn is clocked into
the transmit formatter on the falling edge of TCLKFn
. When the transmit elastic
store is enabled (TESCR.TESE=
1), data on TSERn is clocked into the transmit
elastic store on the falling edge of TSYSCLKn. See the timing dia
grams in Figure
14-5 and Figure 14-6.
TSYNCn/
TSSYNCn
IO
8mA
This pin is only active in external mode (GCR1.MODE=1). GCR1.TSSYNCPE[n]=0
configures this pin to be TSYNCn while TSSYNCPE[n]=1 configures it to be
TSSYNCn.
TSYNCn: Transmit Frame/Multiframe Sync Input/Output
TSYNCn is only used when the transmit elastic store is disabled
(TESCR.TESE=
0). It is internally inverted when TIOCR.
TSYNCINV=1.
When TIOCR.TSIO=0, TSYNC is an input, and a pulse at this pin establishes
either frame or multiframe boundaries for the transmit formatter. TIOCR.TSM
spe
cifies frame (0) or multiframe (1) mode for TSYNCn. The TSYNCn input is
latched on the falling edge of TCLKFn . See the timing diagram in Figure 14-5.
When TIOCR.TSIO=1, TSYNC is an output that pulses at either frame or
multiframe boundaries. TIOCR.TSM
specifies frame (0) or multiframe (1) mode for
TSYNCn. If TSYNCn is configured to output pulses at frame boundaries, it also
can be set to output doublewide pulses at signaling frames when the formatter is in
T1 mode by setting TIOCR.TSDW=1. Th
e TSYNCn output is updated on the rising
edge of TCLKFn . See the timing diagra
m in Figure 14-5.
TSSYNCn: Transmit System Frame/Multiframe Sync Input
TSSYNCn is only used when the transmit elastic store is enabled
(TESCR.TESE=
1). It is internally inverted when TIOCR.TSSYNCINV=1 and is
always an input. A pulse at this pin establishes either frame or multiframe
boundaries for the system side (i.e. cross-connect side) of the transmit elastic
store. TIOCR.TSSM specif
ies frame (0) or multiframe (1) mode for TSSYNCn.
TSSYNCn is latched on the falling edge of TSYSCLKn. See the timing diag
ram in
Figure 14-6.