Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name:
BSRL
Register Description:
BERT Status Register Latched
Register Address:
base address + 0x1C
Bit # 15 14 13 12 11 10 9 8
Name -- -- -- -- -- -- -- --
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Name -- -- -- -- PMSL
BEL BECL OOSL
Default 0 0 0 0 0 0 0 0
The bits in this register are latched status bits. Each bit is set when the associated event occurs and is only cleared
when the CPU writes 1 to it. These bits can create interrupts when enabled by the corresponding bit in the BSRIE
regi
ster.
Bit 3: Performance Monitoring Update Status Latched (PMSL). This bit is set when the BSR.PMS bit transitio
ns
from 0 to 1.
Bit 2: Bit Error Latched (BEL). This bit is set when a bit error is detected.
Bit 1: Bit Error Count Latched (BECL). This bit is set when the BSR.BEC bit transitions from 0 to 1.
Bit 0: O
ut Of Synchronization Latched (OOSL). This bit is set when the BSR.OOS bit cha
nges state.
Register Name:
BSRIE
Register Description:
BERT Status Register Interrupt Enable
Register Address:
base address + 0x20
Bit # 15 14 13 12 11 10 9 8
Name -- -- -- -- -- -- -- --
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Name -- -- -- -- PMSIE BEIE BECIE OOSIE
Default 0 0 0 0 0 0 0 0
Bit 3: Performance Monitoring Update Status Interrupt Enable (PMSIE). This bit enables an interrupt if the
BSRL.PMSL bit is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 2: Bit Error Interrupt Enable (BEIE). This bit enables an interrupt if the BSRL.BEL bit is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 1: Bit Error Count Interrupt Enable (BECIE). This bit enables an interrupt if the BSRL.BECL bit is set
.
0 = interrupt disabled
1 = interrupt enabled
Bit 0: Out Of Synchronization Interrupt Enable (OOSIE). This bit enables an interrupt if the BSRL.OOSL bit is
set.
0 = interrupt disabled
1 = interrupt enabled