Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name:
LDET
Register Description:
LIU Detect
Register Address:
base address + 0x20
Bit # 7 6 5 4 3 2 1 0
Name -- -- -- -- -- -- -- RFAIL
Default 0 0 0 0 0 0 0 0
Bit 0: Receive Failure (RFAIL).
This is a read-only real-time status bit.
0 = No short detected on the RTIP/RRING pin
s
1 = Short detected on the RTIP/RRING pins
11.5.4 BERT Registers
Table 11-23 lists the BERT registers. All addresses not listed in the table are reserved and should be initialized with
a value of 0x00 for proper operation. The base address for the port n BERT is 0x104,400+0x80*(n-1) (where
n=1-8 for DS34T108, n=1-4 for DS34T104, n=1-2 for DS34T102, n=1 only for DS34T101). The BERT block was
originally designed for a 16-bit data bus. In this device, each 16-bit register is mapped to the least significant bytes
of the dword.
Table 11-23. BERT Registers
Addr
Offset
Register Name Description
Read/Write or
Read Only
Page
0x00 BCR BERT Control Register R/W 313
04 BPCR BERT Pattern Configuration Register R/W 314
08 BSPR1 BERT Seed/Pattern Register #1 R/W 315
0C BSPR2 BERT Seed/Pattern Register #2 R/W 315
10 TEICR Transmit Error Insertion Control Register R/W 316
18 BSR BERT Status Register RO 316
1C BSRL BERT Status Register Latched R/W 317
20 BSRIE BERT Status Register Interrupt Enable R/W 317
28 RBECR1 Receive Bit Error Count Register 1 RO 318
2C RBECR2 Receive Bit Error Count Register 2 RO 318
30 RBCR1 Receive Bit Count Register 1 RO 319
34 RBCR2 Receive Bit Count Register 2 RO 319