Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name:
LLSR
Register Description:
LIU Latched Status Register
Register Address:
base address + 0x14
Bit # 7 6 5 4 3 2 1 0
Name JALTC OCC SCC LOSC JALTS OCD SCD LOSD
Default 0 0 0 0 0 0 0 0
The bits in this register are latched status bits. Each bit is set when the associated event occurs and is only cleared
when the CPU writes 1 to it. These bits can create interrupts when enabled by the corresponding bit in the LSIMR
regi
ster.
Bit 7: Jitter Attenuator Limit Trip Clear (JALTC). This latched status bit is set when a jitter attenuator limit trip
condition is removed. See section 10.13.4.
Bit
6: Open Circuit Clear (OCC).
This latched status bit is set when an open circuit condition is removed. See
section 10.13.2.7.
Bit
5: Short Circuit Clear (SCC).
This latched status bit is set when a short circuit condition is removed. See
section 10.13.2.6.
Bit 4: L
oss of Signal Clear (LOSC). This latched status bit is set when a loss-of-signal condition is removed. See
section 10.13.3.6.
Bit 3: Jitter Attenuator Limit Trip Set (JALTS). This latched status bit is set when a jitter attenuator limit trip
condition is detected. See section 10.13.4.
Bit 2
: Open Circuit Detect (OCD).
This latched status bit is set when an open circuit condition is detected on
TTIP/TRING.
This bit is not functional in T1 CSU operating modes (i.e. when LTRCR:T1J1E1S=1 and
LTISR:L[2:0]=10
1, 110 or 111). See section 10.13.2.7.
Bit
1: Short Circuit Detect (SCD).
This latched status bit is set when short circuit condition is detected on
TTIP/TRING.
This bit is not functional in T1 CSU operating mode. See section 10.13.2.6.
Bit 0
: Loss of Signal Detect (LOSD).
This latched status bit is set when a loss-of-signal condition is detected on
RTIP/RRING.
See section 10.13.3.6.