Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name:
LSIMR
Register Description:
LIU Status Interrupt Mask Register
Register Address:
base address + 0x10
Bit # 7 6 5 4 3 2 1 0
Name JALTCIM OCCIM SCCIM LOSCIM JALTSIM OCDIM SCDIM LOSDIM
Default 0 0 0 0 0 0 0 0
This bits in this register mask or enable interrupts caused by the latched status bits in the LLSR regi
ster.
Bit 7: Jitter Attenuator Limit Trip Clear Interrupt Mask (JALTCIM).
0 = Interrupt masked.
1 = Interrupt enabled.
Bit 6: Open Circuit Clear Interrupt Mask (OCCIM).
0 = Interrupt masked.
1 = Interrupt enabled.
Bit 5: Short Circuit Clear Interrupt Mask (SCCIM).
0 = Interrupt masked.
1 = Interrupt enabled.
Bit 4: Loss of Signal Clear Interrupt Mask (LOSCIM).
0 = Interrupt masked.
1 = Interrupt enabled.
Bit 3: Jitter Attenuator Limit Trip Set Interrupt Mask (JALTSIM).
0 = Interrupt masked.
1 = Interrupt enabled.
Bit 2: Open Circuit Detect Interrupt Mask (OCDIM).
0 = Interrupt masked.
1 = Interrupt enabled.
Bit 1: Short Circuit Detect Interrupt Mask (SCDIM).
0 = Interrupt masked.
1 = Interrupt enabled.
Bit 0: Loss of Signal Detect Interrupt Mask (LOSDIM)
.
0 = Interrupt masked.
1 = Interrupt enabled.