Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name:
LRSR
Register Description:
LIU Real-Time Status Register
Register Address:
base address + 0x0C
Bit # 7 6 5 4 3 2 1 0
Name JAO JAU OEQ UEQ JALT SCS OCS LOS
Default 0 0 0 0 0 0 0 0
These bit are read-only real-time status bits.
Bit 7: JA Overflow (JAO). The jitter attenuator FIFO is currently in an overflow state. See section 10.13.4.
Bit 6: JA Un
derflow (JAU). The jitter attenuator FIFO is currently in an underflow state. See section 10.13.4.
Bit 5
: Over Equalized (OEQ). The receiver is over-equalized. This can happen if there is a very large unexpected
resistive loss. This could happen in a monitor mode application if the device is not placed in monitor mode (see
LRISMR.
RMONEN). This indicator provides more qualitative information to the receive loss indicators.
Bit 4: Under Equalized (UEQ). The receiver is under-equalized. A signal with a very high resistive gain is being
applied. This indicator provides more qualitative information to the receive loss indicators.
Bits 3: Jitter Attenuator Limit Trip (JALT). This bit indicates the occurrence of an underflow or an overflow from
the jitter attenuator FIFO. See section 10.13.4.
0 = No FIFO
underflow or overflow event is occurring
1 = A FIFO underflow or overflow event is occurring
Bit 2: Short Circuit Status (SCS).
This bit is set when the LIU detects that the TTIP and TRING outputs are short-
circuited. The load resistance has to be 25
 (typically) or less for a short-circuit to be indicated. See section
10.13.2.6.
Bit 1: O
pen Circuit Status (OCS).
This bit is set when the LIU detects that the TTIP and TRING outputs are open-
circuited. See section 10.13.2.7.
Bit 0: L
oss of Signal Status (LOS).
This bit is set when the LIU detects a loss-of-signal condition on the RTIP
and RRING inputs. See
section 10.13.3.6.