Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name:
LTRCR
Register Description:
LIU Transmit Receive Control Register
Register Addresses:
base address + 0x00
Bit # 7 6 5 4 3 2 1 0
Name RTR RHPM JADS1 JADS0 JAPS1 JAPS0 T1J1E1S LCS
Default 0 0 0 0 0 0 0 0
Bit 7: Receiver Turns Ratio (RTR). This bit specifies the turns ratio for the LIU receiver. Internal termination is
only available with the 1:1 transformer setting. The 2:1 transformer setting requires external termination. See
section 10.13.3.1.
0 = 1:1 turn
s ratio for the receiver
1 = 2:1 turns ratio for the receiver
Bit 6: Receiver Hitless Protection Mode (RHPM). If this bit is set to one, the LIU receiver’s internal termination
circuitry grants control to the RXTSEL
pin, which is used for hitless protection switching under hardware control.
When this bit is set to zero, the LIU receiver’s internal termination circuitry is controlled by software via the
LRISMR.
RIMPON bit for hitless protection switching.
0 = Normal operation using software for hitless protection
1 = Hitless protection switching mode using the RXTSEL pin
Bit 5 to 4
: Jitter Attenuator Depth Select (JADS[1:0]). These bits are used to select the total depth of the jitter
attenuator (JA) FIFO.
JADS1 JADS0 Function
0 0 JA FIFO depth set to 128 bits
0 1 JA FIFO depth set to 64 bits
1 0 JA FIFO depth set to 32 bits
1 1 JA FIFO depth set to 16 bits
Bit 3, 2: Jitter Attenuator Position Select (JAPS[1:0]). These bits are used to select the position of the jitter
attenuator (JA).
JAPS1 JAPS0 Function
0 0 Disable JA
0 1 Insert JA into the Receive path
1 0 Insert JA into the Transmitter path
1 1 Insert JA into the Transmitter path
Bit 1: T1J1E1 Selection (T1J1E1S). This bit configures the LIU for E1 or T1/J1 operation.
0 = E1
1 = T1 or J1
Bit 0: LOS Criteria Selection (LCS). This bit specifies the LIU receiver’s loss-of-signal (LOS) criteria. See section
10.13.3.6.
E1 Mode
0 = G.775
1 = ETSI (30
0233)
T1 / J1 Mode
0 = T1.231
1 = T1.231