Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name:
TBPCS1, TBPCS2, TBPCS3, TBPCS4
Register Description:
Transmit BERT Channel Select Registers
Register Address:
base address + 0x750, 0x754, 0x758, 0x75C
Bit # 7 6 5 4 3 2 1 0
TBPCS1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
TBPCS2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
TBPCS3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
TBPCS4 CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
Bits 7 to 0 (x4): Transmit BERT Port Channel Select for Channels 1 to 32 (CH1 to CH32). These bits specify
for which channels data is sourced from the transmit BERT. Any combination of channels may be selected
simultaneously. See section 10.14.3.
0 = Do n
ot map the selected channel to the transmit BERT port.
1 = Map the selected channel to the transmit BERT Port.
11.5.3 LIU Registers
Table 11-22 lists the LIU registers. All addresses not listed in the table are reserved and should be initialized with a
value of 0x00 for proper operation. The base address for the port n LIU is 0x104,000+0x80*(n-1) (where n=1-8
for DS34T108, n=1-4 for DS34T104, n=1-2 for DS34T102, n=1 only for DS34T101). The LIU block was originally
designed for an 8-bit data bus. In this device, each 8-bit register is mapped to the least significant byte of the
dword.
Table 11-22. LIU Registers
Addr
Offset
Register Name Description
Read/Write or
Read Only
Page
0x00 LTRCR LIU Transmit Receive Control Register R/W 304
04 LTISR LIU Transmit Impedance Selection Register R/W 305
08 LMCR LIU Maintenance Control Register R/W 306
0C LRSR LIU Real-Time Status Register RO 307
10 LSIMR LIU Status Interrupt Mask Register R/W 308
14 LLSR LIU Latched Status Register R/W 309
18 LRSL LIU Receive Signal Level RO 310
1C LRISMR LIU Receive Impedance and Sensitivity Monitor Reg
R/W 311
20 LDET LIU Detect RO 312