Datasheet
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name:
TBCS1, TBCS2, TBCS3, TBCS4
Register Description:
Transmit Blank Channel Select Registers
Register Address:
base address + 0x700, 0x704, 0x708, 0x70C
Bit # 7 6 5 4 3 2 1 0
TBCS1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
TBCS2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
TBCS3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
TBCS4 CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
Bits 7 to 0 (x4): Transmit Blank Channel Select for Channels 1 to 32 (CH1 to CH32). Reset defaults: CH1 to
C24 default to 0 while CH25 to CH32 default to 1. See section 10.10.
0 = Tra
nsmit data from the formatter’s TSER input for this channel
1 = Ignore data from the formatter’s TSER input for this channel
Note that when two or more sequential channels are chosen to be ignored, the transmit slip zone select bit
(TESCR.TSZ
S) should be set to zero. If the blank channels are distributed (such as 1, 5, 9, 13, 17, 21, 25, 29) then
the RSZS bit can be set to one, which may provide a lower occurrence of slips in certain applications.
Register Name:
THSCS1, THSCS2, THSCS3, THSCS4
Register Description:
Transmit Hardware Signaling Channel Select Registers
Register Address:
base address + 0x720, 0x724, 0x728, 0x72C
Bit # 7 6 5 4 3 2 1 0
THSCS1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
THSCS2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
THSCS3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
THSCS4* CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
Bits 7 to 0 (x4): Transmit Hardware Signaling Select for Channels 1 to 32 (CH1 to CH32). These bits
determine which channels have signaling data inserted from the formatter’s TSIG input.
0 = Do not source signaling data for this channel from the TSIG input
1 = Source signaling data for this channel from the TSIG input
*Note that THSCS4 is only used in applications where the system TDM interface is configured for 2.048MHz..
Register Name:
PCL1, PCL2, PCL3, PCL4
Register Description:
Per-Channel Loopback Enable Registers
Register Address:
base address + 0x740, 0x744, 0x748, 0x74C
Bit # 7 6 5 4 3 2 1 0
PCL1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
PCL2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
PCL3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
PCL4 CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25
Bits 7 to 0: Per-Channel Loopback Enable for Channels 1 to 32 (CH1 to CH32). See section 10.11.11.
0 = Loo
pback disabled
1 = Enable loopback. Source data for the channel from the corresponding channel in the receive framer.