Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
301 of 366
Bit 0: Transmit FIFO Not Full Condition (TNF). This real-time status bit is set to 1 when the Tx HDLC FIFO has
at least one byte available to accept new data. The TFBA registe
r reports the actual number of bytes available. See
section 10.12.2.
Register Name:
TFBA
Register Description:
Transmit HDLC FIFO Buffer Available Register
Register Address:
base address + 0x6CC
Bit # 7 6 5 4 3 2 1 0
Name -- TFBA6 TFBA5 TFBA4 TFBA3 TFBA2 TFBA1 TFBA0
Default 0 0 0 0 0 0 0 0
Bits 6 to 0: Transmit FIFO Bytes Available (TFBA[6:0]). TFBA0 is the LSB. This real-time status field indicates
the number of bytes in the Tx HDLC FIFO available to accept new data. See section 10.12.2.
Register Name:
THF
Register Description:
Transmit HDLC FIFO Register
Register Address:
base address + 0x6D0
Bit # 7 6 5 4 3 2 1 0
Name THD7 THD6 THD5 THD4 THD3 THD2 THD1 THD0
Default 0 0 0 0 0 0 0 0
Bit 7 to 0: Transmit HDLC Data (THD[7:0]). A write to this register stores the value written in the Tx HDLC FIFO.
Bit 7 is the MSb. See section 10.12.2.
Register Name:
TDS0M
Register Description:
Transmit DS0 Monitor Register
Register Address:
base address + 0x6EC
Bit # 7 6 5 4 3 2 1 0
Name B1 B2 B3 B4 B5 B6 B7 B8
Default 0 0 0 0 0 0 0 0
Bits 7 to 0: Transmit DS0 Channel Bits (B1 to B8). Transmit data for the channel that has been selected by the
Transmit Channel Monitor Select Register, TDS0SEL. B8 is the LSb of the DS0 channel (last bit to be transmitted).
See section 10.11.9.