Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name:
TCD1
Register Description:
Transmit Code Definition Register 1 (T1 Mode Only)
Register Address:
base address + 0x6B0
Bit # 7 6 5 4 3 2 1 0
Name C7 C6 C5 C4 C3 C2 C1 C0
Default 0 0 0 0 0 0 0 0
This register and TCD2 specify the code to be transmitted when TCR3.TLOOP is set to one. The length of the code
is specified by TCR4.T
C[1:0]. See section 10.11.14.
Bit 7: Transmit Code Definition Bit 7
(C7). First bit of the repeating pattern.
Bit 6: Transmit Code Definition Bit 6 (C6).
Bit 5: Transmit Code Definition Bit 5 (C5).
Bit 4: Transmit Code Definition Bit 4 (C4).
Bit 3: Transmit Code Definition Bit 3 (C3).
Bit 2: Transmit Code Definition Bit 2 (C2). Ignored if a 5 bit length is selected.
Bit 1: Transmit Code Definition Bit 1 (C1). Ignored if a 5 or 6 bit length is selected.
Bit 0: Transmit Code Definition Bit 0 (C0). Ignored if a 5, 6 or 7 bit length is selected.
Register Name:
TCD2
Register Description:
Transmit Code Definition Register 2 (T1 Mode Only)
Register Address:
base address + 0x6B4
Bit # 7 6 5 4 3 2 1 0
Name C7 C6 C5 C4 C3 C2 C1 C0
Default 0 0 0 0 0 0 0 0
This register and TCD1 specify the code to be transmitted when TCR3.TLOOP is set to one. The length of the code
is specified by TCR4.T
C[1:0]. See section 10.11.14.
Bit 7: Transmit Code Definition Bit 7
(C7). Ignored if a 5, 6 or 7 bit length is selected.
Bit 6: Transmit Code Definition Bit 6 (C6). Ignored if a 5, 6 or 7 bit length is selected.
Bit 5: Transmit Code Definition Bit 5 (C5). Ignored if a 5, 6 or 7 bit length is selected.
Bit 4: Transmit Code Definition Bit 4 (C4). Ignored if a 5, 6 or 7 bit length is selected.
Bit 3: Transmit Code Definition Bit 3 (C3). Ignored if a 5, 6 or 7 bit length is selected.
Bit 2: Transmit Code Definition Bit 2 (C2). Ignored if a 5, 6 or 7 bit length is selected.
Bit 1: Transmit Code Definition Bit 1 (C1). Ignored if a 5, 6 or 7 bit length is selected.
Bit 0: Transmit Code Definition Bit 0 (C0). Ignored if a 5, 6 or 7 bit length is selected.
Register Name:
TRTS2
Register Description:
Transmit Real-Time Status Register 2 (HDLC)
Register Address:
base address + 0x6C4
Bit # 7 6 5 4 3 2 1 0
Name - - - - TEMPTY TFULL TLWM TNF
Default 0 0 0 0 0 0 0 0
Bit 3: Transmit FIFO Empty (TEMPTY). This real-time bit is set to 1 when the Tx HDLC FIFO is empty. See
section 10.12.2.
Bit 2: Transmit FIFO Full (TFUL
L). This real-time bit that is set to 1 when the Tx HDLC FIFO is full. See section
10.12.2.
Bit 1: Transmit FIFO Belo
w Low Watermark Condition (TLWM). This real-time status bit is set to 1 when the Tx
HDLC FIFO empties beyond the low watermark specified by THFC.TFLW
M. See section 10.12.2.