Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
3 of 366
10.9.1 TDMoP Interrupt
s .................................................................................................................................. 104
10.9.2 LIU, Framer and BERT Interrupts ......................................................................................................... 106
10.10 ELASTIC STORES AND FRAMER SYSTEM INTERFACE .....................................................................108
10.10.1 Elastic Store Initialization..................................................................................................................... 108
10.10.2 Minimum Delay Mode.......................................................................................................................... 109
10.10.3 Additional Elastic Store Information .................................................................................................... 109
10.11 FRAMERS....................................................................................................................................111
10.11.1 T1 and E1 Framing Formats ............................................................................................................... 111
10.11.2 T1 Transmit Frame Synchronizer........................................................................................................ 115
10.11.3 Signaling.............................................................................................................................................. 115
10.11.4 T1 Datalink .......................................................................................................................................... 118
10.11.5 E1 Datalink .......................................................................................................................................... 120
10.11.6 Maintenance and Alarms..................................................................................................................... 121
10.11.7 E1 Automatic Alarm Generation.......................................................................................................... 123
10.11.8 Error Count Registers.......................................................................................................................... 124
10.11.9 DS0 Monitoring Function..................................................................................................................... 125
10.11.10 Framer and Payload Loopbacks ....................................................................................................... 126
10.11.11 Per-Channel Loopback...................................................................................................................... 126
10.11.12 Per-Channel Idle Code Insertion ....................................................................................................... 126
10.11.13 Digital Milliwatt Code Generation ...................................................................................................... 127
10.11.14 In-Band Loop Code Generation and Detection (T1 Only)................................................................. 127
10.11.15 G.706 Intermediate CRC-4 Recalculation (E1 Only)......................................................................... 128
10.11.16 SLC–96 Operation (T1 Only)............................................................................................................. 128
10.12 HDLC CONTROLLERS .................................................................................................................129
10.12.1 Receive HDLC Controller .................................................................................................................... 130
10.12.2 Transmit HDLC Controller ................................................................................................................... 132
10.13 LINE INTERFACE UNITS (LIU) .......................................................................................................134
10.13.1 LIU Operation ...................................................................................................................................... 135
10.13.2 LIU Transmitter.................................................................................................................................... 136
10.13.3 LIU Receiver........................................................................................................................................ 138
10.13.4 Jitter Attenuator ................................................................................................................................... 140
10.13.5 LIU Loopbacks..................................................................................................................................... 141
10.14 BIT ERROR RATE TEST FUNCTIONS (BERTS)...............................................................................144
10.14.1 BERT General Description .................................................................................................................. 144
10.14.2 BERT Features.................................................................................................................................... 144
10.14.3 BERT Configuration and Monitoring.................................................................................................... 144
10.14.4 BERT Receive Pattern Detection ........................................................................................................ 145
10.14.5 BERT Transmit Pattern Generation .................................................................................................... 147
10.15 LIU - FRAMER CONNECTIONS ......................................................................................................148
11 DEVICE REGISTERS .......................................................................................................................149
11.1 ADDRESSING.................................................................................................................................149
11.2 TOP-LEVEL MEMORY MAP .............................................................................................................150
11.3 GLOBAL REGISTERS ......................................................................................................................151
11.4 TDM-OVER-PACKET REGISTERS....................................................................................................159
11.4.1 Configuration and Status Registers....................................................................................................... 160
11.4.2 Bundle Configuration Tables ................................................................................................................. 174
11.4.3 Counters ................................................................................................................................................ 184
11.4.4 Status Tables......................................................................................................................................... 187
11.4.5 Timeslot Assignment Tables ................................................................................................................. 189
11.4.6 CPU Queues ......................................................................................................................................... 191
11.4.7 Transmit Buffers Pool ............................................................................................................................ 196
11.4.8 Jitter Buffer Control................................................................................................................................ 197
11.4.9 Transmit Software CAS ......................................................................................................................... 201
11.4.10 Receive Line CAS ............................................................................................................................... 203
11.4.11 Clock Recovery ................................................................................................................................... 204
11.4.12 Receive SW Conditioning Octet Select............................................................................................... 205