Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Bit 0: Loss of Transmit Clock Condition (LOTC).
0 = interrupt masked
1 = interrupt enabled
Register Name:
TIM2
Register Description:
Transmit Interrupt Mask Register 2
Register Address:
base address + 0x684
Bit # 7 6 5 4 3 2 1 0
Name - - - TFDLE TUDR TMEND TLWMS TNFS
Default 0 0 0 0 0 0 0 0
The bits in the register are interrupt mask/enable bits for corresponding latched status bits in TLS2.
Bit 4: Tr
ansmit FDL Register Empty (TFDLE). T1 Mode Only.
0 = interrupt masked
1 = interrupt enabled
Bit 3: Transmit FIFO Underrun Event (TUDR).
0 = interrupt masked
1 = interrupt enabled
Bit 2: Transmit Message End Event (TMEND).
0 = interrupt masked
1 = interrupt enabled
Bit 1: Transmit FIFO Below Low Watermark Set Event (TLWMS).
0 = interrupt masked
1 = interrupt enabled
Bit 0: Transmit FIFO Not Full Set Event (TNFS).
0 = interrupt masked
1 = interrupt enabled
Register Name:
TIM3
Register Description:
Transmit Interrupt Mask Register 3 (Synchronizer)
Register Address:
base address + 0x688
Bit # 7 6 5 4 3 2 1 0
Name - - - - - - - LOFD
Default 0 0 0 0 0 0 0 0
The bits in the register are interrupt mask/enable bits for corresponding latched status bits in TLS3.
Bit 0: Lo
ss Of Frame Synchronization Detect (LOFD).
0 = Interrupt Masked
1 = Interrupt Enabled