Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name:
TIIR
Register Description:
Transmit Interrupt Information Register
Register Address:
base address + 0x67C
Bit # 7 6 5 4 3 2 1 0
Name - - - - - TLS3 TLS2 TLS1
Default 0 0 0 0 0 0 0 0
The bits in this register indicate which of the framer latched status registers, TLS1 through TLS3, are curre
ntly
generating interrupt requests (1=interrupt request pending). When an interrupt request occurs, the CPU can read
TIIR to quickly identify the source(s) of the interrupt. Each bit in TIIR automatically clears when there are no
unmasked latched status register bits set in the corresponding TLS register. TLS register bits that have been
masked by a corresponding bit in the TIM regi
sters are also masked from affecting the TIIR bits.
Register Name:
TIM1
Register Description:
Transmit Interrupt Mask Register 1
Register Address:
base address + 0x680
Bit # 7 6 5 4 3 2 1 0
Name
TESF TESEM TSLIP TSLC96
TPDV
TAF
TMF LOTCC LOTC
Default 0 0 0 0 0 0 0 0
The bits in the register are interrupt mask/enable bits for corresponding latched status bits in TLS1.
Bit 7: Transmit Elastic Store Full Event (TESF).
0 = interrupt masked
1 = interrupt enabled
Bit 6: Transmit Elastic Store Empty Event (TESEM).
0 = interrupt masked
1 = interrupt enabled
Bit 5: Transmit Elastic Store Slip Occurrence Event (TSLIP).
0 = interrupt masked
1 = interrupt enabled
Bit 4: Transmit SLC96 Multiframe Event (TSLC96). T1 Mode Only.
0 = interrupt masked
1 = interrupt enabled
Bit 3 (T1 Mode): Transmit Pulse Density Violation Event (TPDV).
0 = interrupt masked
1 = interrupt enabled
Bit 3 (E1 Mode): Transmit Align Frame Event (TAF).
0 = interrupt masked
1 = interrupt enabled
Bit 2: Transmit Multiframe Event (TMF).
0 = interrupt masked
1 = interrupt enabled
Bit 1: Loss of Transmit Clock Clear Condition (LOTCC).
0 = interrupt masked
1 = interrupt enabled