Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name:
TLS1
Register Description:
Transmit Latched Status Register 1
Register Address:
base address + 0x640
Bit # 7 6 5 4 3 2 1 0
Name
TESF TESEM TSLIP TSLC96
TPDV
TAF
TMF LOTCC LOTC
Default 0 0 0 0 0 0 0 0
Bit 7: Transmit Elastic Store Full Event (TESF). This latched status bit is set to 1 when the transmit elastic store
buffer fills and a frame is deleted. TESF is cleared when written with a 1. When TESF is set it can cause an
interrupt request if the corresponding interrupt enable bit is set in the TIM1 regi
ster. See Section 10.10.
Bit 6
: Transmit Elastic Store Empty Event (TESEM). This latched status bit is set to 1 when the transmit elastic
store buffer empties and a frame is repeated. TESEM is cleared when written with a 1. When TESEM is set it can
cause an interrupt request if the corresponding interrupt enable bit is set in the TIM1 regi
ster. See Section 10.10.
Bit 5: Tra
nsmit Elastic Store Slip Occurrence Event (TSLIP). This latched status bit is set to 1 when the
transmit elastic store has either repeated or deleted a frame (i.e. either TESF or TESEM set). TSLIP is cleared
when written with a 1. When TSLIP is set it can cause an interrupt request if the corresponding interrupt enable bit
is set in the TIM1 regi
ster. See Section 10.10.
Bit 4: Tr
ansmit SLC-96 Multiframe Event (TSLC96). T1 Mode Only. When enabled by TCR2-T1.TSLC96, this
latche
d status bit is set once per SLC-96 multiframe (72 frames) to alert the CPU that new data may be written to
the TSLC1-TSLC3
registers. This bit is cleared when written with a 1. When it is set it can cause an interrupt
request if the corresponding interrupt enable bit is set in the TIM1 registe
r. See section 10.11.16.
Bit 3
(T1 Mode): Transmit Pulse Density Violation Event (TPDV). This latched status bit is set to 1 when the
transmit data stream does not meet the ANSI T1.403 requirements for pulse density. TPDV is cleared when written
with a 1. When TPDV is set it can cause an interrupt request if the corresponding interrupt enable bit is set in the
TIM1 regi
ster.
Bit 3 (E1 Mode): Transmit Align Frame Event (TAF). This latched status bit is set to 1every 250
s to alert the
CPU that the TAF and TNAF regi
sters can be updated. It is cleared when written with a 1. When TAF is set it can
cause an interrupt request if the corresponding interrupt enable bit is set in the TIM1 regi
ster. See Section
10.11.5.1.
Bit 2
: Transmit Multiframe Event (TMF). In T1 mode, this latched status bit is set to 1 every 1.5ms on SF (D4)
MF boundaries or every 3ms on ESF MF boundaries. In E1 operation, it t is set every 2ms (regardless of whether
CRC-4 is enabled or not) on transmit multiframe boundaries to alert the CPU that signaling data can be updated.
TMF is cleared when written with a 1. When TMF is set it can cause an interrupt request if the corresponding
interrupt enable bit is set in the TIM1 re
gister.
Bit 1: Loss of Transmit Clock Condition Clear (LOTCC). This latched status bit is set to 1 when a loss of
transmit clock condition has cleared (a clock has been sensed at formatter’s TCLK input). LOTCC is cleared when
written with a 1. When LOTCC is set it can cause an interrupt request if the corresponding interrupt enable bit is set
in the TIM1 registe
r.
Bit 0: Loss of Transmit Clock Condition (LOTC). This latched status bit is set to 1 when the formatter’s TCLK
input has not transitioned for approximately 3 clock periods. LOTC is cleared when written with a 1 and can be
cleared by the CPU even if the condition is still present. When LOTC is set it can cause an interrupt request if the
corresponding interrupt enable bit is set in the TIM1 registe
r.