Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name:
THFC
Register Description:
Transmit HDLC FIFO Control Register
Register Address:
base address + 0x61C
Bit # 7 6 5 4 3 2 1 0
Name - - - - - - TFLWM1 TFLWM2
Default 0 0 0 0 0 0 0 0
Bits 1 to 0: Transmit HDLC FIFO Low Watermark Select (TFLWM[1:0]). See section 10.12.2.
TFLWM
1 TFLWM0 Transmit FIFO Watermark
0 0 4 bytes
0 1 16 bytes
1 0 32 bytes
1 1 48 bytes
Register Name:
TDS0SEL
Register Description:
Transmit DS0 Monitor Select Register
Register Address:
base address + 0x624
Bit # 7 6 5 4 3 2 1 0
Name - - - TCM4 TCM3 TCM2 TCM1 TCM0
Default 0 0 0 0 0 0 0 0
Bits 4 to 0: Transmit Channel Monitor Bits (TCM[4:0]). This field specifies which transmit DS0 channel’s data is
available to be read from the TDS0M register. 00000=channel 1. 11111=channel 32. See section 10.11.9.
Register Name:
TXPC
Register Description:
Transmit Expansion Port Control Register
Register Address:
base address + 0x628
Bit # 7 6 5 4 3 2 1 0
Name
-- -- -- --
-- TBPDIR TBPFUS TBPEN
Default 0 0 0 0 0 0 0 0
Bit 2: Transmit BERT Port Direction Control (TBPDIR).
0 = Normal (line) operation. Tx BERT port sources data into the transmit path (i.e. toward the LIU).
1 = Reverse (system) operation. Tx BERT port sources data into the receive path (i.e. toward the TDMoP
block).
Bit 1: Transmit BERT Port Framed/Unframed Select (TBPFUS). T1 Mode Only. See section 10.14.3.
0 = Do
n’t clock data into the F-bit position (framed)
1 = Clock data into the F-bit position (unframed)
Bit 0: Transmit BERT Port Enable (TBPEN). See section 10.14.3.
0 = Tra
nsmit BERT Port is not active
1 = Transmit BERT Port is active.