Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name:
TCR4
Register Description:
Transmit Control Register 4 (T1 Mode Only)
Register Address:
base address + 0x618
Bit # 7 6 5 4 3 2 1 0
Name uALAW BINV1 BINV0 TJBEN TRAIM TAISM TC1 TC0
Default 0 0 0 0 0 0 0 0
Bit 7: u-Law or A-Law Digital Milliwatt Code Select (uALAW).
0 = u-law code is inserted based on TDMWE re
gisters.
1 = A-law code is inserted based on TDMWE re
gisters.
Bits 6 to 5: Transmit Bit Inversion (BINV[1:0])
00 = No inversion
01 = Invert framing
10 = Invert signaling
11 = Invert payload
Bit 4: Transmit Jammed Bit 8 Enable (TJBEN). When set to 1, this bit enables the transmit jammed bit 8 function
to operate for the channels specified by the TJBE re
gisters.
0 = Disabled
1 = Enabled
Bits 3: Transmit RAI Mode (TRAIM). T1 ESF Mode Only. Determines the pattern sent when TCR1-T1.TRAI is
set to 1.
0 = No
rmal RAI
1 = RAI-CI (ANSI T1.403)
Bits 2: Transmit AIS Mode (TAISM). Determines the pattern sent when TCR1-T1. TAIS is set to 1.
0 = No
rmal AIS (unframed all ones)
1 = AIS-CI (ANSI T1.403)
Bits 1 to 0: Transmit Code Length Definition Bits (TC[1:0]). This field specifies the length of the code in the
TCD1 and TCD2 regi
sters. See section 10.11.14.
00 = 5 bits
01 = 3 or 6 bits
10 = 7 bits
11 = 1, 2, 4 or 8 bits