Datasheet
____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name:
TESCR
Register Description:
Transmit Elastic Store Control Register
Register Address:
base address + 0x614
Bit # 7 6 5 4 3 2 1 0
Name TDATFMT - - TSZS TESALGN TESR TESMDM TESE
Default 0 0 0 0 0 0 0 0
Bit 7: Transmit Channel Data Format (TDATFMT).
0 = 64kBps (data contained in all 8 bits)
1 = 56kBps (data contained in 7 out of the 8 bits)
Bit 6: Reserved, must be set to zero for proper operation.
Bit 5: Reserved, must be set to zero for proper operation.
Bit 4: Transmit Slip Zone Select (TSZS). This bit determines the minimum distance allowed between the elastic
store read and write pointers before forcing a controlled slip. This bit is only applies during T1 to E1 or E1 to T1
conversion applications. See section 10.10.
0 = Force a slip at 9 bytes or less of separation (used for clustered blank channels)
1 = Force a slip at 2 bytes or less of separation (used for distributed blank channels)
Bit 3: Transmit Elastic Store Align (TESALGN). Changing this bit from zero to one forces the transmit elastic
store’s write and read pointers to a minimum separation of half a frame. No action is taken if the pointer separation
is already greater or equal to half a frame. If pointer separation is less than half a frame, the command is executed
and the data is disrupted. This bit should be toggled after TSYSCLK has been applied and is stable. Must be
cleared and set again for a subsequent align. See section 10.10.1.
Bit
2: Transmit Elastic Store Reset (TESR). Changing this bit from zero to one forces the read pointer into the
same frame that the write pointer is exiting, minimizing the delay through the elastic store. If this command should
place the pointers within the slip zone (specified by TSZS above), then an immediate slip occurs and the pointers
move back to opposite frames. This bit should be toggled after TSYSCLK has been applied and is stable. Do not
leave this bit set high. See section 10.10.1.
Bit 1: Tr
ansmit Elastic Store Minimum Delay Mode (TESMDM). See section 10.10.2.
0 = Elasti
c store operates at full two frame depth
1 = Elastic store operates at 32-bit depth
Bit 0: Transmit Elastic Store Enable (TESE). See section 10.10.
0 = Elasti
c store is bypassed
1 = Elastic store is enabled