Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name:
TIOCR
Register Description:
Transmit I/O Configuration Register
Register Address:
base address + 0x610
Bit # 7 6 5 4 3 2 1 0
Name
TCLKINV TSYNCINV TSSYNCINV TSCLKM TSSM TSIO TSDW TSM
Default 0 0 0 0 0 0 0 0
Bit 7: TCLKF Invert (TCLKINV). See the TCLK signal going into the transmit formatter in Figure 6-1.
0 = No inve
rsion
1 = Invert TCLK signal
Bit 6: TSYNC Invert (TSYNCINV). See the TSYNC signal from the transmit formatter in Figure 6-1.
0 = No inve
rsion
1 = Invert TSYNC
Bit 5: TSSYNC Invert (TSSYNCINV). See the TSSYNC signal going into the transmit formatter in Figure 6-1.
0 = No inve
rsion
1 = Invert TSSYNC
Bit 4: TSYSCLK Mode Select (TSCLKM). See the TSYSCLK signal going into the transmit formatter in Figure 6-1.
See also 10.10.3.1.
0 = TSYSCLK is 1.544M
Hz
1 = TSYSCLK is 2.048MHz
Bit 3: TSSYNC Mode Select (TSSM). Selects frame or multiframe mode for the TSSYNC signal going into the
transmit formatter in Figure 6-1.
0 = Frame mode
1 = Multiframe mode
Bit 2: TSYNC I/O Select (TSIO). Figure 6-1.Co
nfigures the direction of the TSYNC signal going into/out-of the
transmit formatter in Figure 6-1.
0 = TSYN
C is an input
1 = TSYNC is an output
Bit 1: TSYNC Double-Wide (TSDW). See the TSYNC out signal from the transmit formatter in Figure 6-1. (N
ote:
this bit must be set to zero when TSM = 1 or when TSIO = 0)
0 = Do not pulse double-wide in signaling frames
1 = Do pulse double-wide in signaling frames
Bit 0: TSYNC Mode Select (TSM). Selects frame or multiframe mode for the TSYNC pin. See the TSYNC out
signal going out-of the transmit formatter in Figure 6-1.
0 = Fra
me mode
1 = Multiframe mode