Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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Register Name:
TCR3
Register Description:
Transmit Control Register 3
Register Address:
base address + 0x60C
Bit # 7 6 5 4 3 2 1 0
Name ODF -- TCSS1 TCSS0 MFRS TFM IBPV TLOOP
CRC4R
Default 0 0 0 0 0 0 0 0
Bit 7: Output Data Format (ODF). See the pos/dat and neg signals in the receive path in Figure 6-1.
0 = Bipolar data (AMI, HDB3 or B8ZS format) is output on the pos and neg signals.
1 = NRZ data is output from on the pos/dat signal. The neg signal is not used.
Bit 6: Reserved, must be set to zero for proper operation.
Bits 5, 4: Transmit Clock Source Select 1, 0 (TCSS[1:0]).
TCSS1 TCSS0 Transmit Clock Source
0 0 The formatter TCLK input is always the source of transmit clock.
0 1
Switch to the clock present on the receive framer’s RCLK input when the
signal at the formatter’s TCLK input fails to transition for channel time (8 bits)
1 0 Reserved
1 1
Use the signal present on the receive framer’s RCLK input as the transmit
clock and ignore the TCLK input to the transmit formatter.
Bit 3: Multiframe Reference Select (MFRS). This bit selects the source for the transmit formatter multiframe
boundary.
0 = Normal Operation. Transmit multiframe boundary is determined by ‘line-side’ counters referenced to
the Tx formatter’s TSYNC signal when TSYNC is an input. Free-running when TSYNC is an output.
1 = Pass-Forward Operation. Tx multiframe boundary determined by ‘system-side’ counters referenced to
the Tx formatter’s TSSYNC signal, which is then ‘passed forward’ to the line side clock domain. This
mode can only be used when the transmit elastic store is enabled with TSYSCLK frequency-locked to
TCLK.(i.e. no frame slips allowed). This mode must be used to allow Tx hardware signaling insertion
while the Tx elastic store is enabled.
Bit 2: Transmit Frame Mode Select (TFM). T1 Mode Only.
0 = ESF framing mode
1 = SF (D4) framing mode
Bit 1: Insert BPV (IBPV). A zero-to-one transition on this bit causes a single bipolar violation (BPV) to be inserted
into the transmit data stream. After this bit has been toggled from a 0 to a 1, the device waits for the next
occurrence of three consecutive ones to insert the BPV. This bit must be cleared and set again for a subsequent
error to be inserted.
Bit 0 (T1 Mode): Transmit Loop Code Enable (TLOOP). See Section 10.11.14.
0 = Tra
nsmit data normally
1 = Replace normal transmitted data with repeating code as defined in registers TCD1 an
d TCD2
Bit 0 (E1 Mo
de): CRC-4 Recalculate (CRC4R). See Section 0.
0 = Transmit CRC-4 generation and insertion operates in normal mode
1 = Transmit CRC-4 generation operates according to G.706 Intermediate Path Recalculation method.