Datasheet

____________________________________________________ DS34T101, DS34T102, DS34T104, DS34T108
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PIN NAME
(1)
TYPE
(2)
PIN DESCRIPTION
CLK_MII_RX I MII Receive Clock Input
MII_RXD[3:0] I MII Receive Data Inputs
MII_RX_DV I MII Receive Data Valid Input
MII_RX_ERR I MII Receive Error Input
MII_COL I MII Collision Input
MII_CRS I MII Carrier Sense Input
MDC O PHY Management Clock Output
MDIO IOpu PHY Management Data Input/Output
Global Clocks
CLK_SYS_S I System Clock Selection Input
CLK_SYS I System Clock Input: 25, 50 or 75MHz
CLK_CMN I Common Clock Input (for common clock mode also known as differential mode)
CLK_HIGH I Clock High Input (for adaptive clock recovery machines and E1/T1 master clocks)
MCLK I Master Clock Input (for E1/T1 master clocks)
CPU Interface
H_CPU_SPI_N Ipu Host Bus Interface (1=Parallel Bus, 0=SPI Bus)
DAT_32_16_N Ipu Data Bus Width (1=32-bit , 0=16-bit)
H_D[31:1] IO Host Data Bus
H_D[0] / SPI_MISO IO Host Data LSb or SPI Data Output
H_AD[24:1] I Host Address Bus
H_CS_N I Host Chip Select (Active Low)
H_R_W_N / SPI_CP I Host Read/Write Control or SPI Clock Phase
H_WR_BE0_N / SPI_CLK I Host Write Enable Byte 0 (Active Low) or SPI Clock
H_WR_BE1_N / SPI_MOSI I Host Write Enable Byte 1 (Active Low) or SPI Data Input
H_WR_BE2_N / SPI_SEL_N I Host Write Enable Byte 2 or SPI Chip Select (Active Low)
H_WR_BE3_N / SPI_CI I Host Write Enable Byte 3 (Active Low) or SPI Clock Invert
H_READY_N Oz Host Ready Output (Active Low)
H_INT[1:0] O Host Interrupt Outputs. H_INT[0] for TDMoP. H_INT[1] for LIU and Framer
JTAG Interface
JTRST_N Ipu JTAG Test Reset
JTCLK Ipd JTAG Test Clock
JTMS Ipu JTAG Test Mode Select
JTDI Ipu JTAG Test Data Input
JTDO Oz JTAG Test Data Output
Reset and Factory Test Pins
RST_SYS_N Ipu System Reset (Active Low)
HIZ_N I High Impedance Enable (Active Low)
SCEN Ipd Used for factory tests.
STMD Ipd Used for factory tests.
MBIST_EN I Used for factory tests.
MBIST_DONE O Used for factory tests.
MBIST_FAIL O Used for factory tests
TEST_CLK O Used for factory tests.
TST_CLD I Used for factory tests.
TST_Tm, TST_Rm O m = A , B or C. Used for factory tests. DS34T104 only.
Power and Ground
DVDDC P 1.8V Core Voltage for Framers and TDM-over-Packet Digital Logic (17 pins)
DVDDIO P 3.3V for I/O Pins (16 pins)
DVSS P Ground for Framers, TDM-over-Packet and I/O Pins (31 pins)
DVDDLIU P 3.3V for LIU Digital Logic (2 pins)
DVSSLIU P Ground for LIU Digital Logic (2 pins)
ATVDDn P 3.3 V for LIU Transmitter Analog Circuits (8pins)
ATVSSn P Ground for LIU Transmitter Analog Circuits (8 pins)
ARVDDn P 3.3 V for LIU Receiver Analog Circuits (8 pins)
ARVSSn P Ground for LIU Receiver Analog Circuits (8 pins)
ACVDD1, ACVDD2 P 1.8V for CLAD Analog Circuits
ACVSS1, ACVSS2 P Ground for CLAD Analog Circuits